參數(shù)資料
型號(hào)： CS5364-CQZR
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 11/42頁(yè)
文件大?。?/td> 0K
描述： IC ADC 4CH 114DB 216KHZ 48-LQFP
標(biāo)準(zhǔn)包裝： 2,000
位數(shù)： 24
采樣率（每秒）： 216k
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 580mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個(gè)差分，單極
配用： CDB5364-ND - EVALUATION BOARD FOR CS5364
DS625F4
19
CS5364
4. APPLICATIONS
4.1
Power
CS5364 features five independent power pins that power various functional blocks within the device and
allow for convenient interfacing to other devices. Table 1 shows what portion of the device is powered from
each supply pin. Please refer to “Recommended Operating Conditions” on page 10 for the valid range of
each power supply pin. The power supplied to each power pin can be independent of the power supplied to
any other pin.
To meet full performance specifications, the CS5364 requires normal low-noise board layout. The “Typical
Connection Diagram” on page 9 shows the recommended power arrangements, with the VA pins connected
to a clean supply. VD, which powers the digital filter, may be run from the system logic supply, or it may be
powered from the analog supply via a single-pole decoupling filter.
Decoupling capacitors should be placed as near to the ADC as possible, with the lower value high-frequen-
cy capacitors placed nearest to the device leads. Clocks should be kept away from the FILT+ and VQ pins
in order to avoid unwanted coupling of these signals into the device. The FILT+ and VQ decoupling capac-
itors must be positioned to minimize the electrical path to ground.
The CDB5364 evaluation board demonstrates optimum layout for the device.
4.2
Control Port Mode and Stand-Alone Operation
4.2.1
Stand-Alone Mode
In Stand-Alone Mode, the CS5364 is programmed exclusively with multi-use configuration pins. This mode
provides a set of commonly used features, which comprise a subset of the complete set of device features
offered in Control Port Mode.
To use the CS5364 in Stand-Alone Mode, the configuration pins must be held in a stable state, at valid logic
levels, and RST must be asserted until the power supplies and clocks are stable and valid. More informa-
tion on the reset function is available in Section 4.5 on page 22.
4.2.2
Control Port Mode
In Control Port Mode, all features of the CS5364 are available. Four multi-use configuration pins become
software pins that support the IC or SPI bus protocol. To initiate Control Port Mode, a controller that sup-
ports IC or SPI must be used to enable the internal register functionality. This is done by setting the CP-
EN bit (Bit 7 of the Global Control Port Register). Once CP-EN is set, all of the device configuration pins
are ignored, and the internal register settings determine the operating modes of the part. Figure 4.13 on
page 30 provides detailed information about the IC and SPI bus protocols.
Power Supply Pin
Pin Name
Pin Number
Functional Block
VA
4, 9
Analog Core
VX
20
Crystal Oscillator
VD
33
Digital Core
VLS
28
Serial Audio Interface
VLC
35
Control Logic
Table 1. Power Supply Pin Definitions
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CS5364-DQZR 功能描述:音頻模/數(shù)轉(zhuǎn)換器 IC IC 114dB 192kHz 4ch ADC w/TDM Intrfc RoHS:否 制造商:Wolfson Microelectronics 轉(zhuǎn)換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風(fēng)格: 封裝 / 箱體: 封裝:
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