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參數(shù)資料
| 型號(hào)： | CS5364-CQZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 24/42頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 4CH 114DB 216KHZ 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 216k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 580mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個(gè)差分，單極 |
| 配用： | CDB5364-ND - EVALUATION BOARD FOR CS5364 |
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30
DS625F4
CS5364
4.13
Control Port Operation
The Control Port is used to read and write the internal device registers. It supports two industry standard
formats, IC and SPI. The part is in IC format by default. SPI Mode is selected if there is ever a high-to-low
transition on the AD0/CS pin after the RST pin has been restored high.
In Control Port Mode, all features of the CS5364 are available. Four multi-use configuration pins become
software pins that support the IC or SPI bus protocol. To initiate Control Port Mode, a controller that sup-
ports IC or SPI must be used to enable the internal register functionality. This is done by setting the
CP-EN bit (Bit 7 of the Global Control Port Register). Once CP-EN is set, all of the device configuration pins
are ignored, and the internal register settings determine the operating modes of the part.
4.13.1
SPI Mode
In SPI Mode, CS is the CS5364 chip select signal; CCLK is the control port bit clock (input into the CS5364
from a controller); CDIN is the input data line from a controller; CDOUT is the output data line to a controller.
Data is clocked in on the rising edge of CCLK and is supplied on the falling edge of CCLK.
To write to a register, bring CS low. The first seven bits on CDIN form the chip address and must be
1001111. The eighth bit is a read/write indicator (R/W), which should be low to write. The next eight bits
form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated.
The next eight bits are the data that will be placed into the register designated by the MAP. During writes,
the CDOUT output stays in the Hi-Z state. It may be externally pulled high or low with a 47 k
Ω resistor, if
desired.
There is a MAP auto-increment capability, which is enabled by the INCR bit in the MAP register. If INCR is
a zero, the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will auto-
increment after each byte is read or written, allowing block reads or writes of successive registers.
To read a register, the MAP has to be set to the correct address by executing a partial write cycle that fin-
ishes (CS high) immediately after the MAP byte. The MAP auto-increment bit (INCR) may be set or not, as
desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W) high.
The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT will leave the high
impedance state). If the MAP auto-increment bit is set to 1, the data for successive registers will appear
consecutively
.
Figure 16. SPI Format
MA P
MSB
LSB
DATA
by te 1
by te n
R/W
AD D R ESS
CH IP
ADDRESS
CH I P
CD I N
CC L K
CS
CD O U T
MSB
LSB MSB
LSB
1001111
MAP = Memory Address Pointer, 8 bits, MSB first
High Impedance
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