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參數(shù)資料
| 型號(hào)： | CS4341-CZZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 11/34頁 |
| 文件大小： | 0K |
| 描述： | IC DAC STER 24BIT 96KHZ 16TSSOP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 90mW |
| 工作溫度： | -10°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | 96k |
| 產(chǎn)品目錄頁面： | 756 (CN2011-ZH PDF) |
| 其它名稱： | 598-1050-5 |
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CS4341
DS298F5
19
4.4
De-Emphasis
The device includes on-chip digital de-emphasis. The Mode Control (address 01h) bits select either the
32, 44.1 or 48 kHz de-emphasis filter. Figure 20 shows the de-emphasis curve for Fs equal to 44.1 kHz.
The frequency response of the de-emphasis curve will scale proportionally with changes in sample
rate, Fs. Please see section 6.2.3 for the desired de-emphasis control.
De-emphasis is only available in Single-Speed Mode.
4.5
Power-Up Sequence
1) Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the
appropriate frequencies, as discussed in section 4.2. In this state, the control port is reset to its default
settings and VQ will remain low.
2) Bring RST high. The device will remain in a low power state with VQ low.
3) Load the desired register settings while keeping the PDN bit set to 1.
4) Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 S when
the POR bit is set to 0. If the POR bit is set to 1, see section 4.6 for a complete description of power-
up timing.
4.6
Popguard Transient Control
The CS4341 uses Popguard technology to minimize the effects of output transients during power-up and
power-down. This technology, when used with external DC-blocking capacitors in series with the audio
outputs, minimizes the audio transients commonly produced by single-ended single-supply converters. It
is activated inside the DAC when RST is enabled/disabled and requires no other external control, aside
from choosing the appropriate DC-blocking capacitors.
4.6.1
Power-Up
When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to
AGND. Following a delay of approximately 1000 sample periods, each output begins to ramp to-
ward the quiescent voltage. Approximately 10,000 LRCK cycles later, the outputs reach VQ and
audio output begins. This gradual voltage ramping allows time for the external DC-blocking capac-
itors to charge to the quiescent voltage, minimizing the power-up transient.
Gain
dB
-10dB
0dB
Frequency
T2 = 15 s
T1=50 s
F1
F2
3.183 kHz
10.61 kHz
Figure 20. De-Emphasis Curve
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CS4341-CZZR | 功能描述:數(shù)模轉(zhuǎn)換器- DAC IC 24bit 96kHz 101dB Stereo DAC w/VC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| CS4341-KS | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 24-bit 96kHz 101dB Stereo DAC w/VC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| CS4341-KSR | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 24-bit 96kHz 101dB Stereo DAC w/VC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| CS4341-KSZ | 制造商:Cirrus Logic 功能描述:24-BIT, 96 KHZ STEREO DAC WITH VOL CNTRL - Bulk 制造商:Cirrus Logic 功能描述:IC DAC 24BIT SRL 96KHZ 16-SOIC 制造商:Cirrus Logic 功能描述:24Bit 96kHz 101dB Stereo DAC |
| CS4341-KSZR | 制造商:Cirrus Logic 功能描述:DAC DUAL DELTA-SIGMA 24BIT 16SOIC - Tape and Reel |
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