參數(shù)資料
型號(hào): CS2100P-DZZR
廠(chǎng)商: CIRRUS LOGIC INC
元件分類(lèi): PLL合成/DDS/VCOs
中文描述: PHASE LOCKED LOOP, 30 MHz, PDSO10
封裝: 3 MM, LEAD FREE, MO-187, MSOP-10
文件頁(yè)數(shù): 24/25頁(yè)
文件大?。?/td> 223K
代理商: CS2100P-DZZR
CS2100-OTP
8
DS841F2
PLL PERFORMANCE PLOTS
Test Conditions (unless otherwise specified): VD = 3.3 V; TA =25°C; CL =15pF; fCLK_OUT = 12.288 MHz;
fCLK_IN = 12.288 MHz; Sample size = 10,000 points; Base Band Jitter (100 Hz to 40 kHz); AuxOutSrc[1:0] =11.
1
10
100
1,000
10,000
0.1
1
10
100
1,000
10,000
Input Jitter Frequency (Hz)
M
a
x
In
p
u
tJ
itte
r
L
e
v
e
l
(u
s
e
c
)
1 Hz Bandwidth
128 Hz Bandwidth
1
10
100
1000
10000
-60
-50
-40
-30
-20
-10
0
10
Input Jitter Frequency (Hz)
J
it
te
rTr
an
sf
er
(
d
B)
1 Hz Bandwidth
128 Hz Bandwidth
Figure 2. CLK_IN Sinusoidal Jitter Tolerance
Figure 3. CLK_IN Sinusoidal Jitter Transfer
Samples size = 2.5M points; Base Band Jitter (10Hz to 40kHz).
Figure 4. CLK_IN Random Jitter Rejection and Tolerance
0.01
0.1
1
10
100
1000
0.01
0.1
1
10
100
1000
Input Jitter Level (nsec)
O
u
tput
Ji
tt
e
rLevel
(
n
sec)
1 Hz Bandwidth
128 Hz Bandwidth
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