參數(shù)資料
型號(hào)： CS2100P-DZZR
廠商： CIRRUS LOGIC INC
元件分類： PLL合成/DDS/VCOs
中文描述： PHASE LOCKED LOOP, 30 MHz, PDSO10
封裝： 3 MM, LEAD FREE, MO-187, MSOP-10
文件頁(yè)數(shù)： 10/25頁(yè)
文件大小： 223K
代理商： CS2100P-DZZR
CS2100-OTP
18
DS841F2
5.7.2
M2 Mode Pin Functionality
M2 usage is mapped to one of the optional special functions via the M2Config[2:0] global parameter. De-
pending on what M2 is mapped to, it will either act as an output enable/disable pin or override certain mod-
al parameters. Figure 15 summarizes the available options and the following sections will describe each
option in more detail.
Figure 15. M2 Mapping Options
5.7.2.1
M2 Configured as Output Disable
If M2Config[2:0] is set to either ‘000’, ‘001’, or ‘010’, M2 becomes an output disable pin for one or
both output pins. If M2 is driven ‘low’, the corresponding output(s) will be enabled, if M2 is driven
‘high’, the corresponding output(s) will be disabled.
5.7.2.2
M2 Configured as R-Mod Enable
If M2Config[2:0] is set to ‘011’, M2 becomes the R-Mod enable pin. It should be noted that M2 is
the only way to enable R-Mod. Even though the RModSel[1:0] modal parameter can be set arbi-
trarily for each configuration set, it will not take effect unless enabled via M2. If M2 is driven ‘low’,
R-Mod will be disabled, if M2 is driven ‘high’ R-Mod will be enabled.
5.7.2.3
M2 Configured as AuxOutSrc Override
If M2Config[2:0] is set to ‘111’, M2 when driven ‘high’ will override the AuxOutSrc[1:0] modal pa-
rameter and force the AUX_OUT source to PLL Clock Output. When M2 is driven ‘low’, AUX_OUT
will function according to AuxOutSrc[1:0].
M2 pin
Disable CLK_OUT and AUX_OUT pins
Disable AUX_OUT pin
Disable CLK_OUT pin
RModSel[1:0] Modal Parameter Enable
Force AuxOutSel[1:0] = 10 (PLL Clock Out)
Reserved
M2Config[2:0] global parameter
000
001
010
011
100
101
110
111
Reserved
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