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參數(shù)資料

型號：	CS2100P-DZZR
廠商：	CIRRUS LOGIC INC
元件分類：	PLL合成/DDS/VCOs
中文描述：	PHASE LOCKED LOOP, 30 MHz, PDSO10
封裝：	3 MM, LEAD FREE, MO-187, MSOP-10
文件頁數(shù)：	12/25頁
文件大?。?/td>	223K
代理商：	CS2100P-DZZR

CS2100-OTP

DS841F2

2

TABLE OF CONTENTS

1. PIN DESCRIPTION ................................................................................................................................. 4

2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 5

3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6

RECOMMENDED OPERATING CONDITIONS .................................................................................... 6

ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6

DC ELECTRICAL CHARACTERISTICS ................................................................................................ 6

AC ELECTRICAL CHARACTERISTICS ................................................................................................ 7

PLL PERFORMANCE PLOTS ............................................................................................................... 8

4. ARCHITECTURE OVERVIEW ............................................................................................................... 9

4.1 Delta-Sigma Fractional-N Frequency Synthesizer ........................................................................... 9

4.2 Hybrid Analog-Digital Phase Locked Loop ...................................................................................... 9

5. APPLICATIONS ................................................................................................................................... 11

5.1 One Time Programmability ............................................................................................................ 11

5.2 Timing Reference Clock Input ........................................................................................................ 11

5.2.1 Internal Timing Reference Clock Divider ............................................................................... 11

5.2.2 Crystal Connections (XTI and XTO) ...................................................................................... 12

5.2.3 External Reference Clock (REF_CLK) .................................................................................. 12

5.3 Frequency Reference Clock Input, CLK_IN ................................................................................... 12

5.3.1 Adjusting the Minimum Loop Bandwidth for CLK_IN ............................................................ 13

5.4 Output to Input Frequency Ratio Configuration ............................................................................. 14

5.4.1 User Defined Ratio (RUD) ..................................................................................................... 14

5.4.2 Ratio Modifier (R-Mod) .......................................................................................................... 15

5.4.3 Effective Ratio (REFF) .......................................................................................................... 15

5.4.4 Ratio Configuration Summary ............................................................................................... 15

5.5 PLL Clock Output ........................................................................................................................... 16

5.6 Auxiliary Output .............................................................................................................................. 17

5.7 Mode Pin Functionality ................................................................................................................... 17

5.7.1 M1 and M0 Mode Pin Functionality ....................................................................................... 17

5.7.2 M2 Mode Pin Functionality .................................................................................................... 18

5.7.2.1 M2 Configured as Output Disable .............................................................................. 18

5.7.2.2 M2 Configured as R-Mod Enable .............................................................................. 18

5.7.2.3 M2 Configured as AuxOutSrc Override ..................................................................... 18

5.8 Clock Output Stability Considerations ............................................................................................ 19

5.8.1 Output Switching ................................................................................................................... 19

5.8.2 PLL Unlock Conditions .......................................................................................................... 19

5.9 Required Power Up Sequencing for Programmed Devices ........................................................... 19

6. PARAMETER DESCRIPTIONS ........................................................................................................... 20

6.1 Modal Configuration Sets ............................................................................................................... 20

6.1.1 R-Mod Selection (RModSel[1:0]) ...........................................................................................20

6.1.2 Auxiliary Output Source Selection (AuxOutSrc[1:0]) ............................................................. 21

6.2 Ratio 0 - 3 ...................................................................................................................................... 21

6.3 Global Configuration Parameters ................................................................................................... 21

6.3.1 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 21

6.3.2 Reference Clock Input Divider (RefClkDiv[1:0]) .................................................................... 21

6.3.3 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 22

6.3.4 Low-Frequency Ratio Configuration (LFRatioCfg) ................................................................ 22

6.3.5 M2 Pin Configuration (M2Config[2:0]) ................................................................................... 22

6.3.6 Clock Input Bandwidth (ClkIn_BW[2:0]) ................................................................................ 22

7. CALCULATING THE USER DEFINED RATIO .................................................................................... 23

7.1 High Resolution 12.20 Format ....................................................................................................... 23

7.2 High Multiplication 20.12 Format ................................................................................................... 23

8. PROGRAMMING INFORMATION ........................................................................................................ 24

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