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| 型號(hào)： | CS2100P-DZZR |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | PLL合成/DDS/VCOs |
| 中文描述： | PHASE LOCKED LOOP, 30 MHz, PDSO10 |
| 封裝： | 3 MM, LEAD FREE, MO-187, MSOP-10 |
| 文件頁數(shù)： | 16/25頁 |
| 文件大?。?/td> | 223K |
| 代理商： | CS2100P-DZZR |
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Rev. 09-25-07
Page 24
SMSC COM20019I
DATASHEET
Table 6.2 - Write Register Summary
ADDR
MSB
WRITE
LSB
REGISTER
00
RI/TR1
0
EXCNAK
RECON
NEW
NEXTID
TA/
TTA
INTERRUPT
MASK
01
C7
C6
C5
C4
C3
C2
C1
C0
COMMAND
02
RD-
DATA
AUTO-
INC
0
A10
A9
A8
ADDRESS
PTR HIGH
03
A7
A6
A5
A4
A3
A2
A1
A0
ADDRESS
PTR LOW
04
D7
D6
D5
D4
D3
D2
D1
D0
DATA
05
0
SUB-AD2
SUB-
AD1
SUB-
AD0
SUBADR
06
RESET
CCHEN
TXEN
ET1
ET2
BACK-
PLANE
SUB-
AD1
SUB-
AD0
CONFIG-
URATION
07-0
TID7
TID6
TID5
TID4
TID3
TID2
TID1
TID0
TENTID
07-1
NID7
NID6
NID5
NID4
NID3
NID2
NID1
NID0
NODEID
07-2
P1-
MODE
FOUR
NAKS
0
RCV-
ALL
CKP3
CKP2
CKP1
SLOW-
ARB
SETUP1
07-3
0
TEST
07-4
RBUS-
TMG
0
EF
NO-
SYNC
RCN-
TM1
RCN-
TM0
SETUP2
6.2
INTERNAL REGISTERS
The COM20019I contains 14 internal registers. Tables 2 and 3 illustrate the COM20019I register map. All
undefined bits are read as undefined and must be written as logic "0".
6.2.1
Interrupt Mask Register (IMR)
The COM20019I is capable of generating an interrupt signal when certain status bits become true. A write
to the IMR specifies which status bits will be enabled to generate an interrupt. The bit positions in the IMR
are in the same position as their corresponding status bits in the Status Register and Diagnostic Status
Register. A logic "1" in a particular position enables the corresponding interrupt. The Status bits capable of
generating an interrupt include the Receiver Inhibited bit, New Next ID bit, Excessive NAK bit,
Reconfiguration Timer bit, and Transmitter Available bit. No other Status or Diagnostic Status bits can
generate an interrupt.
The six maskable status bits are ANDed with their respective mask bits, and the results are ORed to
produce the interrupt signal. An RI or TA interrupt is masked when the corresponding mask bit is reset
to logic "0", but will reappear when the corresponding mask bit is set to logic "1" again, unless the interrupt
status condition has been cleared by this time. A RECON interrupt is cleared when the "Clear Flags"
command is issued. An EXCNAK interrupt is cleared when the "POR Clear Flags" command is issued. A
New Next ID interrupt is cleared by reading the Next ID Register. The Interrupt Mask Register defaults to
the value 0000 0000 upon hardware reset.
6.2.2
Data Register
This read/write 8-bit register is used as the channel through which the data to and from the RAM passes.
The data is placed in or retrieved from the address location presently specified by the address pointer.
The contents of the Data Register are undefined upon hardware reset. In case of READ operation, the
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