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| 型號(hào)： | CR16HCT5 |
| 文件頁(yè)數(shù)： | 77/157頁(yè) |
| 文件大?。?/td> | 1256K |
| 代理商： | CR16HCT5 |
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UnETI
Enable Transmitter Interrupt. This read/write
bit, when set to 1, enables generation of an in-
terrupt when the hardware sets the UnTBE bit.
Enable Receiver Interrupt. This read/write bit,
when set to 1, enables generation of an inter-
rupt when the hardware sets the UnRBF bit.
Enable Receive Error Interrupt. This read/write
bit, when set to 1, enables generation of an in-
terrupt when the hardware sets the UnERR bit
in the UnSTAT register.
UnERI
UnEEI
18.4
The USART baud rate is determined by the system clock fre-
quency and the values programmed into the UnPSR and Un-
BAUD registers. Unless the system clock frequency is an
exact multiple of the desired baud rate, there will be a small
amount of error in the resulting baud rate clock.
The method of baud rate calculation depends on whether the
USART is configured to operate in the asynchronous or syn-
chronous mode.
BAUD RATE CALCULATIONS
18.4.1
The equation for calculating the baud rate in asynchronous
mode is:
Baud Rate in Asynchronous Mode
where BR is the baud rate, SYS_CLK is the system clock, N
is the value of the baud rate divisor + 1, and P is the prescaler
divide factor selected by the value in the UnPSR register.
Assuming a system clock of 5 MHz and a desired baud rate
of 9600, the NxP term according to the equation above is:
The NxP term is then divided by each Prescaler Factor from
Table 19 to obtain a value closest to an integer. The factor for
this example is 6.5.
The baud rate register is programmed with a baud rate divi-
sor of 4 (N = baud rate divisor +1). This produces a baud
clock of:
Note that the percent error is much lower than would be pos-
sible without the non-integer prescaler factor. Refer to the ta-
ble below for more examples.
18.4.2
The equation for calculating the baud rate in synchronous
mode is:
Baud Rate in Synchronous Mode
where BR is the baud rate, SYS_CLK is the system clock, N
is the value of the baud rate divisor + 1, and P is the prescaler
divide factor selected by the value in the UnPSR register.
Use the same procedure to determine the values of N and P
as in the asynchronous mode. In this case, however, only in-
teger prescaler values are allowed.
BR
CLK
N
×
P
×
)
-16
=
N
P
×
6
×
10
9600
×
)
16
)
------5
32.552
=
=
N
6.5
32.552
5.008 (N = 5)
=
=
BR
×
6
×
10
5
(
)
6.5
16
×
(
)
--------5
9615.385
=
=
%
error
-9615.9600
9600
–
(
)
0.16
=
=
System
Clock
Desired
Baud Rate
N
P
Actual
Baud Rate
Percent
Error
4 MHz
5 MHz
10 MHz
20 MHz
9600
9600
19200
19200
2
5 6.5
5 6.5
5
13
9615.385
9615.385
19230.769
19230.769
0.16
0.16
0.16
0.16
13
BR
CLK
2
N
P
×
)
----------_
=
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