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| 型號(hào)： | CR16HCT5 |
| 文件頁(yè)數(shù)： | 71/157頁(yè) |
| 文件大小： | 1256K |
| 代理商： | CR16HCT5 |
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18.0
USART
The USART module is a full-duplex Universal Synchronous/
Asynchronous Receiver/Transmitter that supports a wide
range of software-programmable baud rates and data for-
mats. It handles automatic parity generation and several er-
ror detection schemes. There are one or two independent
USART modules in each device, depending on the package
type.
Each USART module offers the following features:
— Full-duplex double-buffered receiver/transmitter
— Synchronous or asynchronous operation
— programmable
baud
[2*(1+2^11)*16] up to SYSCLK/2 for USART config-
ured to run in synchronous mode
— programmable
baud
[16*(1+2^11)*16] up to SYSCLK/16 for USART config-
ured to run in asynchronous mode
— Programmable framing formats: seven, eight, or nine
data bits; one or two stop bits; and odd, even, mark,
space, or no parity
— Hardware parity generation for data transmission and
parity check for data reception
— Interrupts on “transmit ready” and “receive ready” con-
ditions, separately enabled
— Software-controlled break transmission and detection
— Internal diagnostic capability
— Automatic detection of parity, framing, and overrun er-
rors
rate
from
SYS_CLK/
rate
from
SYS_CLK/
18.1
Figure 32 is a block diagram of the USART module showing
the basic functional units in the USART:
— Transmitter
— Receiver
— Baud Rate Generator
— Control and Error Detection
Note:
In the description of the USART, the lower-case letter
“n” represents the USART number. For example, TDXn
means TDX1 or TDX2.
The Transmitter block consists of an 8-bit transmit shift reg-
ister and an 8-bit transmit buffer. Data bytes are loaded in
parallel from the buffer into the shift register and then shifted
out serially on the TDXn pin.
The Receiver block consists of an 8-bit receive shift register
and an 8-bit receive buffer. Data is received serially on the
RDXn pin and shifted into the shift register. Once eight bits
have been received, the contents of the shift register are
transferred in parallel to the receive buffer.
The Transmitter and Receiver blocks both contain exten-
sions for 9-bit data transfers, as required by the 9-bit and
loopback operating modes.
The Baud Rate Generator generates the clock for the syn-
chronous and asynchronous operating modes. It consists of
two registers and a two-stage counter. The registers are
used to specify a prescaler value and a baud rate divisor. The
first stage of the counter divides the USART clock based on
the value of the programmed prescaler to create a slower
clock. The second stage of the counter divides the output of
FUNCTIONAL OVERVIEW
the first stage based on the programmed baud rate divisor to
create the baud rate clock.
The Control and Error Detection block contains the USART
control registers, control logic, error detection circuit, parity
generator/checker, and interrupt generation logic. The con-
trol registers and control logic determine the data format,
mode of operation, clock source, and type of parity used. The
error detection circuit generates parity bits and checks for
parity, framing, and overrun errors.
18.2
The USART has two basic modes of operation: synchronous
and asynchronous. In addition, there are two special-
purpose synchronous and asynchronous modes, called at-
tention and diagnostic. This section describes the operating
modes of the USART.
USART OPERATION
18.2.1
The asynchronous mode of the USART enables the device
to communicate with other devices using just two communi-
cation signals: transmit and receive.
In the asynchronous mode, the transmit shift register (TSFT)
and the transmit buffer (UnTBUF) double-buffer the data for
transmission. To transmit a character, a data byte is loaded
in the UnTBUF register. The data is then transferred to the
TSFT register. While the TSFT is shifting out the current
character (LSB first) on the TDXn pin, the UnTBUF register
is loaded by software with the next byte to be transmitted.
When TSFT finishes transmission of the last stop bit of the
current frame, the contents of UnTBUF are transferred to the
TSFT register and the Transmit Buffer Empty flag (UnTBE) is
set. The UnTBE flag is automatically reset by the USART
when the software loads a new character into the UnTBUF
register. During transmission, the UnXMIP bit is set high by
the USART. This bit is reset only after the USART has sent
the last stop bit of the current character and the UnTBUF reg-
ister is empty. The UnTBUF register is a read/write register.
The TSFT register is not user accessible.
In asynchronous mode, the input frequency to the USART is
16 times the baud rate. In other words, there are 16 clock cy-
cles per bit time. In asynchronous mode the baud rate gen-
erator is always the USART clock source.
The receive shift register (RSFT) and the receive buffer (Un-
RBUF) double buffer the data being received. The USART
receiver continuously monitors the signal on the RDXn pin for
a low level to detect the beginning of a start bit. Upon sensing
this low level, the USART waits for seven input clock cycles
and samples again three times. If all three samples still indi-
cate a valid low, then the receiver considers this to be a valid
start bit, and the remaining bits in the character frame are
each sampled three times, around the mid-bit position. For
any bit following the start bit, the logic value is found by ma-
jority voting, i.e. the two samples with the same value define
the value of the data bit. Figure 33 illustrates the process of
start bit detection and bit sampling.
Serial data input on the RDXn pin is shifted into the RSFT
register. Upon receiving the complete character, the contents
of the RSFT register are copied into the UnRBUF register
and the Receive Buffer Full flag (UnRBF) is set. The UnRBF
Asynchronous Mode
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