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| 型號(hào)： | CR16HCT5 |
| 文件頁(yè)數(shù)： | 41/157頁(yè) |
| 文件大?。?/td> | 1256K |
| 代理商： | CR16HCT5 |
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41
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and asserts the “Good Low Speed Clk” signal, thus indicating
that the slow clock is stable.
For systems that do not require a reduced power consump-
tion mode, the external crystal network may be omitted for
the slow clock. In that case, the slow clock can be created by
dividing the main clock by a prescaler factor. The prescaler
circuit consists of a fixed divide-by-2 counter and a program-
mable 8-bit prescaler register. This allows a choice of clock
divisors ranging from 2 to 512. The resulting slow clock fre-
quency must not exceed 100 kHz.
A software-programmable multiplexer selects either the
prescaled main clock or the 32.768 kHz oscillator as the slow
clock. Upon reset, the prescaled main clock is selected, en-
suring that the slow clock is always present initially. Selection
of the 32.768 kHz oscillator as the slow clock disables the
clock prescaler, which allows the CLK1 oscillator to be turned
off during power-save operation, thus reducing power con-
sumption and radiated emissions. This can be done only if
the module detects a togging low-speed oscillator. If the low-
speed oscillator is not operating, the prescaler remains avail-
able as the slow clock source.
12.4
The Power-On Reset circuit generates a system reset signal
upon power-up and holds the signal active for a period of
time to allow the crystal oscillator to stabilize. The circuit de-
tects a power turn-on condition, which presets the 14-bit tim-
er to 3FFF hex. Once oscillation starts and the clock
becomes active, the timer starts counting down. When the
count reaches zero, the 14-bit timer stops counting and the
internal reset signal is deactivated (unless the RESET pin is
held low).
The circuit sets a power-on reset flag bit upon detection of a
power-on condition. The CPU can read this flag to determine
whether a reset was caused by a power-up or by the RESET
input.
Note:
Power-On Reset circuit cannot be used to detect a
drop in the supply voltage.
POWER-ON RESET
12.5
An active-low reset input pin called RESET allows the device
to be reset at any time. When the signal goes low, it gener-
ates an internal system reset signal that remains active until
the RESET signal goes high again.
EXTERNAL RESET
12.6
The Dual Clock and Reset module (CLK2RES) contains two
registers: the Clock and Reset Control register (CRCTRL)
and the Slow Clock Prescaler register (PRSSC).
DUAL CLOCK AND RESET REGISTERS
12.6.1
Clock and Reset Control Register (CRCTRL) is a byte-wide
read/write register that contains the power-on reset flag and
selects the type of slow clock. The register format is shown
below.
7
6
5
4
Reserved
Clock and Reset Control Register (CRCTRL)
SCLK
Slow Clock Select. When this bit is set to 1, the
32.728 kHz oscillator is used for the slow clock.
When this bit is cleared to 0, the prescaled
main clock is used for the slow clock. Upon re-
set, this bit is cleared to 0.
Power-On Reset. This bit is set to 1 by the
hardware when a power-on condition is detect-
ed, allowing the CPU to determine whether a
power-up has occurred. The CPU can clear
this bit to 0 but cannot set it to 1. Any attempt
by the CPU to set this bit is ignored.
POR
12.7
SLOW CLOCK PRESCALER REGISTER
(PRSSC)
The Slow Clock Prescaler (PRSSC) register is a byte-wide
read/write register that holds the clock divisor used to gener-
ate the slow clock from the main clock. The format of the reg-
ister is shown below.
7
6
5
4
SCDIV
SCDIV
Slow Clock Divisor. If the clock divider is en-
abled (CRCTRL.SCLK=0), the main clock is di-
vided by (SCDIV+1)*2 to produce the slow
system clock. Upon reset, PRSSC register is
set to FF hex.
12.8
SLOW CLOCK PRESCALER 1 REGISTER
(PRSSC1)
The Slow Clock Prescaler 1 (PRSSC1) register is a byte-
wide read/write register that holds the clock divisor used to
generate the two additional slow clocks from the high-speed
clock. Upon reset, the register is set to 00. The format of the
register is shown below.
7
4
SCDIV2
SCDIV1
Slow Clock Divisor 1. The main clock is divided
by (SCDIV1+1) to obtain the first slow system
clock.
Slow Clock Divisor 2. The main clock is divided
by (SCDIV2+1) to obtain the second slow sys-
tem clock.
SCDIV1
3
2
1
0
POR
SCLK
3
2
1
0
3
0
SCDIV1
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