參數(shù)資料
型號(hào)： CPS1027-J
英文描述： Telecommunication IC
中文描述： 通信集成電路
文件頁(yè)數(shù)： 54/64頁(yè)
文件大?。?/td> 870K
代理商： CPS1027-J
CSP1027 Voice Band Codec for
Cellular Handset and Modem Applications
Data Sheet
January 2002
Agere Systems Inc.
54
10 Analog Characteristics and Requirements
(continued)
10.4 Miscellaneous
* The codec is intended to drive a floating 2 k
load, such as a telephone handset speaker, or 1 k
loads ac-coupled to ground on both ana-
log outputs. Since the codec outputs AOUTP and AOUTN have common-mode dc voltage, ac coupling must be used if there is a dc path to
V
DD
or V
SS
(ground) through the load.
Table 22. D/A Frequency Response Relative to 1 kHz Output Level (f
OS
= 1 MHz and f
S
= 8 kHz)
Frequency
High-Pass Filter Enabled
(HPFE = 0)
Min
50 Hz
—
60 Hz
—
100 Hz
–34
200 Hz
–12
300 Hz
–0.25
3000 Hz
–0.25
3400 Hz
–0.9
4000 Hz
—
4600 Hz
—
8000 Hz
—
High-Pass Filter Disabled
(HPFE = 1)
Min
–0.25
–0.25
–0.25
–0.25
–0.25
–0.25
–0.9
—
—
—
Unit
Max
–40
–40
–18
0
0.25
0.25
0.25
–6
–35
–45
Max
0.25
0.25
0.25
0.25
0.25
0.25
0.25
–6
–35
–45
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Table 23. Other Analog Characteristics and Requirements*
Parameter
D/A Differential Output Resistance (0 kHz to 4 kHz)
D/A Single-ended Output Resistance (0 kHz to 4 kHz)
Analog-to-Digital Power Supply Rejection Ratio at 3 kHz
Digital-to-Analog Power Supply Rejection Ratio at 3 kHz
Analog Input Coupling Capacitor Input Leakage Current
Idle Channel Noise at Analog-to-Digital Output with Input Gain Setting of
500 mVp or 160 mVp
Idle Channel Noise at Digital-to-Analog Output
A/D to D/A and D/A to A/D Crosstalk
Digital-to-Analog Image Frequency Attenuation Above 4600 Hz
Digital-to-Analog Output Amplifier Differential Swing for 2 k
Load
Codec Filter Group Delay for Frequencies Less than 800 Hz
Codec Filter Group Delay for Frequencies Greater than 800 Hz
Recovery Time of Digital-to-Analog Output Due to a Change from Inac-
tive Mode to Active Mode, Muted to Not Muted, or Change in Output
Gain (See
cioc0
register, ACTIVE, MUTE, OGSEL.)
Recovery Time of Analog-to-Digital PCM Output and V
REG
Due to a
Change from Inactive Mode to Active Mode (See
cioc0
register,
ACTIVE.)
Recovery Time of Analog Circuits Due to a Change in Input Select or
Input Range (See
cioc0
register, INSEL and IRSEL.)
Allowable CLK Input Jitter
Allowable CLK Frequency Error
Min
—
—
30
40
—
—
Max
12
6
—
—
30
–65
Unit
dB
dB
nA
dBm0
—
—
35
—
—
—
—
300
–65
—
1.5
2.8
0.8
100
μVrms
dB
dB
Vrms
ms
ms
ms
—
600
ms
—
100
ms
–5
–1
5
1
ns
%
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