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| 型號： | CPS1027-J |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 21/64頁 |
| 文件大小： | 870K |
| 代理商： | CPS1027-J |
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Agere Systems Inc.
21
Data Sheet
January 2002
CSP1027 Voice Band Codec for
Cellular Handset and Modem Applications
4 Architectural Information
(continued)
Figure 22. Passive Communication and Connections
4.6.4 Passive I/O Configuration (SMODE[1:0] = 00)
The passive SIO configuration allows the user maxi-
mum flexibility in interfacing the CSP1027 to a variety
of system hardware configurations. It requires that the
user supply a serial input/output clock (IOCK) and per-
form data transfers at the sampling rate, f
S
. Serial data
transfers can be made to occur at the sampling rate by
applying a clock that is synchronous with the codec
clock, ICLK, to the SYNC pin or by polling the codec
STATUS flag, which indicates that the
cdx(A/D)
register
is full and the
cdx(D/A)
register is empty. The STATUS
flag appears on DO when the SADD pin selects a con-
trol word.
Passive SIO is selected by setting both SMODE1 and
SMODE0 low. The input/output clock (IOCK) is an input
and the common input/output load, SYNC, (equivalent
to a DSP16A's ILD and OLD tied together) is also an
input. Serial data input (DI) is an input and serial data
output, DO, is an output. The serial address (SADD) is
an input, which determines if the transfer is to the con-
trol registers,
cioc
[0:3], or the data register,
cdx(D/A)
.
A high-to-low transition of SYNC pin signal, latched by
the next rising edge of IOCK, initiates the start of an
input and output transaction. If the CSP1027's output
buffer,
cdx(A/D)
, is full, it will be loaded into the output
shift register (
osr
) and shifted out on the DO pin. The
CSP1027 shifts in the data from the DI pin into its input
shift register (
isr
). A serial transmit address on the
SADD line is received simultaneously with data on the
DI line. If SADD is high for the first 15 bits, correspond-
ing to a zero serial transmit address, this causes the
isr
to be latched into
cdx(D/A)
after 16 bits have been
shifted in. If SADD is low for any of the first 15 bits, cor-
responding to a nonzero transmit address, this causes
the
isr
to be latched into
cioc
[0:3] and also changes
the output data stream on DO to display the internal
codec STATUS flag. If SADD is low for any clock cycle,
while not involved in a serial transaction, the codec
STATUS flag is displayed on the DO pin until the next
data transfer.
An example of the passive SIO configuration is shown
in Figure 22. The DSP supplies both the serial clock
(IOCK) and the sampling synchronization signal to
SYNC, or polls the internal codec STATUS flag to deter-
mine when a data transmission is needed. This config-
uration allows the user maximum flexibility in interfacing
the CSP1027 to a variety of other system hardware
configurations.
A/D DATA
CLOCK
CONTROL/DATA ADDRESS
INPUT/OUTPUT LOAD
D
I
I
O
D
O
D
I
S
S
D
DSP
CSP1027
SMODE0
SMODE1
SMODE2
D/A DATA
S
5-7590 (F)
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