- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382908 > CPS1027-J Telecommunication IC PDF資料下載
參數(shù)資料
| 型號： | CPS1027-J |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 17/64頁 |
| 文件大?。?/td> | 870K |
| 代理商： | CPS1027-J |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當(dāng)前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
Agere Systems Inc.
17
Data Sheet
January 2002
CSP1027 Voice Band Codec for
Cellular Handset and Modem Applications
4 Architectural Information
(continued)
CDIV0 has values of 1 or 2, ADJMOD is 0 or 1, and
ADJMOD ranges from 1 to 127, with 0 selecting no
clock adjust. RSTB going low sets CDIV0 to ÷2. ICLK0
is active while RSTB is low and synchronized by RSTB
going high.
4.5.4 Clock Divider 1
Figure 20. Clock Divider 1
The CDIV1 field in
cioc1
(see Table 8 on page 27) sets
a clock divider that generates the CKO1 output clock.
This general-purpose clock output can be used for
clocking another codec in the system, such as the
CSP1084. The ability to phase adjust the output clock
and the codec sampling clock simultaneously is an
important feature. CDIV1 ranges from 1 to 31, with 0
disabling the output. RSTB going low sets CDIV1
to ÷16. CKO1 is active while RSTB is low and synchro-
nized by RSTB going high.
4.5.5 Sampling Clocks Generation
Figure 21. Sampling Clocks Generation
The oversampling codec clock CK
OS
, typically 1 MHz,
is used in the front sections of the A/D and the back
sections of the D/A. The lower-frequency codec clock,
CK
S
, typically 8 kHz, is the sample clock at the output
of the A/D and the input to the D/A. The sampling clock
frequency, f
S
, is the oversampling clock frequency, f
OS
,
divided by 125 (the fixed oversampling ratio). The
divide by 125 must remain fixed, since it is constrained
by the architecture of the codec digital filters. Many sys-
tems, however, have fixed high-frequency clocks and
fixed sampling clocks, so it is necessary to have a great
deal of flexibility in the creation of the codec clock CK
S
.
The CSP1027 solves this problem in a unique way, by
providing a programmable, fractional divider, F1.
F1 is the programmable ratio between ICLK0 and
CK
OS
. The equation for F1 is:
where 3
≤
M
≤
64, 0
≤
N
≤
62, and S = {1, –1};
or M = 2, 0
≤
N
≤
62, and S = 1;
or M = 1, N = 0, and S = 1.
M is encoded by CDIV3 (see Table 3 on page 18), N is
encoded by CDIF0, CDIF1, and CDIF2 (see Table 5 on
page 19), and S is encoded by CDIFS (see Table 4 on
page 18).
CK
S
is generated by dividing CK
OS
by 125. The fre-
quency of CK
S
can be described by:
Note that when N = 0, ICLK0 is simply divided by the
integer M to create the oversampling clock, CK
OS
. This
is the preferred method for generating the sampling
clock. If N
≠
0, the fractional division results in an over-
sampling clock, CK
OS
, whose period varies with time
such that the average period is the desired fraction.
This variation in the oversampling clock period is mini-
mized by the clock generator but can cause distortion
in the codec. Because the denominator of the fraction
is fixed at 125, the period of the sampling clock, CK
S,
will be an integer multiple of the period of the internal
clock, ICLK0, and will not vary. This is more clearly
shown by the following equation:
The expanded equation below explains what is hap-
pening in the time domain:
During each sampling period,
, there are (125 – N)
oversampling clock cycles of period
and N
oversampling clock cycles of period
. The N
oversampling clock cycles are evenly distributed
among the (125 – N) oversampling clock cycles to min-
imize the distortion due to oversampling clock cycles of
differing period. The values for CDIF[0—2] in Table 5
on page 19 have been selected to achieve the even dis-
tribution.
÷
CDIV1
ICLK0
CKO1
5-7587 (F)
÷
F1
ICLK0
CK
S
÷
125
CK
OS
CDIFS, CDIF0, DSIF1,
CDIF2, CDIV3
5-7586 (F)
F1
M
S
125
---------
×
+
=
f
S
f
OS
125
÷
f
ICLK
0
M
S
125
---------
×
+
÷
125
÷
=
=
0
f
S
----------------
125
M
×
(
)
S
N
×
(
)
+
=
1
f
S
----
125
N
–
(
)
f
ICLK
0
----------------
×
N
f
ICLK
0
---------+
)
×
+
=
1
f
S
----
f
ICLK
0
----------------
f
ICLK
0
---------+
)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CPS1027-S | Telecommunication IC |
| CPS1087 | Analog IC |
| CPU16RM | M68HC16 Family CPU16 Reference Manual |
| CQ202-4M | 4.0 AMP TRIAC 600 THRU 800 VOLTS |
| CQ202-4B | TRIAC|200V V(DRM)|4A I(T)RMS|TO-202 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CPS1027-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| CPS1033A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CPS1036A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CPS1037A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CPS1038A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。