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參數(shù)資料
| 型號(hào)： | CPM100 |
| 英文描述： | CPM100 - DISCONTINUED PRODUCT. No longer recommended for new design. |
| 中文描述： | CPM100 -已停產(chǎn)產(chǎn)品。不再推薦用于新設(shè)計(jì)。 |
| 文件頁(yè)數(shù)： | 9/11頁(yè) |
| 文件大?。?/td> | 152K |
| 代理商： | CPM100 |
9
CMP100
capacitors for high frequency filtering if necessary. Electro-
lytic capacitors are not recommended because their high
frequency response is poor.
Separate the Analog and Digital Signals
Digital signal paths entering or leaving the layout should
have minimum length to minimize crosstalk to analog wir-
ing. Stray capacitive feedback from digital outputs to the
analog input may cause the outputs to appear fuzzy well
after the outputs have changed. Keep analog signals as far
away as possible from digital signals. If they must cross,
cross them at right angles. Coaxial cable may be necessary
for analog inputs in some situations.
MEASURING
CMP100 PERFORMANCE
USING AN OSCILLOSCOPE
Oscilloscope probes should be matched to the oscilloscope.
Use an oscilloscope with at least 400MHz bandwidth.
Be sure the probe compensation is adjusted properly. Im-
proper compensation will result in apparent overshoot and/
or ringing if undercompensated, and an apparent slow edge
if overcompensated. If the probe ground lead is too long, the
output may appear distorted and oscillatory. Use probes with
short (less than one inch) ground straps or use a coaxial
cable connection instead of a probe. Do not use X1 or
“straight” probes. Their bandwidth is 20MHz or less and
capacitive loading is high. The best method is to use 50
matched terminations as shown in Figures 2 and 3.
MEASURING PROPAGATION DELAY
Figure 2 shows a circuit configuration used for evaluating
propagation delay. It uses 50
matched terminations be-
tween the instruments and the CMP100 for best signal
integrity. An HP8130A Pulse Generator is used for the
analog input and for the latching signals. The oscilloscope is
an HP54503A 500MHz Digitizing Oscilloscope. This setup
was used to generate the dynamic performance waveforms
in the Typical Performance Curves section.
MEASURING LOGIC TIMING
Figure 3 shows the circuit configuration used for evaluating
logic propagation delay. The logic input LE1 has been added
to the circuit of Figure 2.
FIGURE 3. Circuit for Evaluating Logic Timing.
Q
1
ACOM
V
REF 2
Analog
In
V
REF 1
LE
1
LE
1
Q
1
Q
2
Q
2
LE
2
LE
2
2
3
V+
11
12
14
13
4
5
16
16.6
16.6
16.6
Scope
To 50
Generator
From 50
+5V
1μF
0.1μF
16.6
16.6
16.6
16.6
To
50
Scope
1
15
9
7
6
–5.2V
0.1μF
1μF
1μF
0.1μF
66.5
66.5
–4V
CMP100
16.6
From 50
Generator
To 50
Scope
49.9
16.6
16.6
00
1
00
1
DCOM
PWR
COM
V–
49.9
10
8
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