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參數(shù)資料
| 型號： | CPM100 |
| 英文描述： | CPM100 - DISCONTINUED PRODUCT. No longer recommended for new design. |
| 中文描述： | CPM100 -已停產(chǎn)產(chǎn)品。不再推薦用于新設(shè)計。 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大小： | 152K |
| 代理商： | CPM100 |
7
CMP100
The t
performance of CMP100 is illustrated in the Typical
Performance Curves.
Minimum Hold Time, t
t
is the minimum time after the positive transition of the
Latch Enable (LE) that an analog input signal must remain
unchanged in order to be acquired and held at the outputs.
t
H
= 0 for CMP100.
LOGIC PERFORMANCE DEFINITIONS
Latch Enable to Output High Delay, t
t
is the propagation delay of latch logic circuits measured
from the 50% point of the Latch Enable signal (LE) High-
to-Low transition to the 50% point of an output (Q) Low-to-
High transition.
Latch Enable to Output Low Delay, t
t
is the propagation delay of latch logic circuits meas-
ured from the 50% point of the Latch Enable signal High-to-
Low transition to the 50% point of an output (Q) High-to-
Low transition.
Minimum Latch Enable Pulse Width, t
t
is the minimum time that the Latch Enable (LE) must be
High in order to acquire and hold an input signal change.
The actual timing performance of CMP100 is illustrated in
the Typical Performance Curves.
OPERATING
CONSIDERATIONS
INPUT VOLTAGE
Input reference voltages V
and V
may vary from
–12V to +12V. The frequency-compensated analog input
network can also swing from –12V to +12V.
Care must be taken to be sure that the Maximum Differential
Input Voltage is not exceeded. That is, the voltage between
Analog In and V
or between Analog In and V
must
not exceed
±
25V. If this voltage is exceeded by 1 or 2 volts,
even momentarily, emitter-base voltage breakdown of the
input transistors will occur and cause a permanent shift of
the offset voltage, V
, to an out-of-spec value. However,
the CMP100 will continue to function and will not be
destroyed.
Input voltages to the CMP100 of uncontrolled magnitude
may occur during system power-up. Take care to assure that
the Absolute Maximum Differential Input Voltage is not
exceeded during power-up.
DRIVING SOURCE IMPEDANCE
An apparent slow response of the CMP100 may be due a
combination of high source impedance and stray capacitance
to ground at the analog input. An R-C combination of 1k
source resistance and 10pF to ground results in a 10ns time
constant—more than double the typical response time of the
CMP100.
THE LATCH FUNCTION
The latch function is used for sampling the state of the
outputs and holding them until the output can be processed.
Figure 1 shows a timing diagram for differential input latch
enable controls, LE and LE. The latches of the CMP100 are
transparent type latches. If LE is Low (LE is High), the Q
outputs indicate the sign of the input difference voltage.
When LE goes High (LE Low), the comparator outputs are
held at the current state.
When the analog input signal passes through the reference
level, the comparator output Q changes, after a time of t
or t
. However, if the output is to be latched, the input
signal must have crossed the threshold for a time t
(set-up
time) before the rising edge of LE occurs in order to capture
the correct output state. On the other hand, in order to
capture a correct output state just before it changes, it is
necessary to maintain that output state for t
, (hold time)
after the rising edge of LE. t
H
= 0 for CMP100.
A minimum latch pulse width of t
is needed to capture the
state of narrow pulses. See the Typical Performance Curves
for an example of sampling a narrow pulse.
10k ECL LOGIC
If the latching function is not used, the Latch Enable inputs
(LE
and LE
) should be returned to an ECL High voltage
(–0.8V) or to Digital Common (0V). LE
and LE
should
be returned to an ECL Low level (–1.8V), to an ECL bias
voltage (–1.3V) or to the –2V 50
load pull-down power
supply. Connecting an ECL input to –5.2V may create a
marginal transistor emitter-base breakdown situation over
the ambient temperature range and is not recommended.
If a single (non-differential) ECL logic input is used,
connect the complementary input to an ECL bias voltage
(–1.3V).
100k ECL LOGIC
The negative power supply, V–, of the CMP100 can be
operated at –4.5V. The common mode input range of the
analog and reference inputs will be reduced to +12V to
–7.5V. Output levels are not affected by changing the V–
power supply voltage to –4.5V.
TTL INPUTS
The operating common mode range of a logic input is –2V
to +2V. Thus one can bias the logic inputs to use them with
TTL inputs if the High input level is maintained below +2V.
In this case, the complementary logic input should be biased
at the TTL threshold of +1.4V.
LEVEL SHIFTING ECL to TTL
The ECL outputs can be translated to TTL using a Motorola
MC10125 Quad ECL-TTL translator. The logic delay t
and t
and the propagation delay t
PDL
and t
PDH
will be
increased by the delay of the translator.
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