
10
CMP100
CMP100 APPLICATIONS
ATE PIN RECEIVER
A typical ATE pin receiver application using CMP100 is
illustrated in Figure 4. The reference inputs, V
and V
are driven by D/A converters (Figure 5) while analog input
is driven directly from the device under test (DUT).
WINDOW COMPARATOR
Because of its high speed, the CMP100 can be used to make
timing measurements on modest-speed digital or high-speed
analog waveforms. When the outputs of the CMP100 are
combined with a NOR gate, a true window comparator
function is implemented. Refer to gate G3 of Figure 6. The
output pulse width generated by an input signal passing
through the reference levels can be measured. This could be
for a rise-time/fall-time measurement (setting the reference
levels at 10% and 90% of the signal height) of a modest
speed digital waveform, or for the width (and hence the
value) of an analog ramp moving between two values from
an integrating type signal detector.
PULSE RECOVERY
The window comparator function can also be used to recon-
struct pulses that have been degraded. Positive and/or nega-
tive reference levels can be set up to detect both High and
Low levels of the pulse.
A plot of the response of CMP100 to a narrow pulse with
V
= 0V is shown in the Typical Performance Curves
section.
DETECTING TRANSIENTS
CMP100 can be connected to Detect and Hold transient
occurrences above and below threshold voltages set by
V
and V
as illustrated in Figure 6. The outputs of
comparator 1 and comparator 2 are fed back to their LE
inputs in order to self-latch their outputs. The Reset control
is used to “unlock” the outputs after the transient occurrence
has been read. The output NOR gate G3 combines CMP100
outputs into a single-output window comparator function.
FIGURE 5. Dual DAC7802 (12-bit port), DAC7801 (8-bit port) or DAC7800 (serial port) D/A Converters Supply Reference
Inputs to the CMP100. For higher resolution use DAC725, dual 16-bit D/A converter.
REF102
2
+V
CC
4
6
5
1
INA105
3
2
6
+5V
+10V
To V
and/or
V
REFB
REFA
3
2
1
23
24
18
6
21
4
12
22
DAC A
DB11
DB0
Data
Inputs
DAC7802
+5V
V
REFA
V
DD
DAC B
DGND
V
REFB
I
OUTB
R
FBB
AGND
I
OUTA
R
FBA
10pF
10pF
A
2
V
REF2
A
1
V
REF1
Analog In
12
11
14
15
1
3
2
10
8 7
6
LE
1
LE
1
LE
2
LE
2
Q
1
Q
1
Q
2
Q
2
A
1
, A
2
are 1/2 OPA2107.
E
0
= E
1
/E
2
, ±0.01%
C
D
D/A control circuitry omitted for clarity.
CMP100
FIGURE 4. Typical ATE Pin Receiver Application.
Driver
Receiver
CMP100
D/A
D/A
D/A
D/A
ATE
Computer
Active
Load
D/A
D/A
Device
Under
Test
Parametric Measurement Unit