參數(shù)資料
型號(hào): CP2110-F01-GM
廠商: SILICON LABORATORIES
元件分類: 總線控制器
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, QCC24
封裝: 4 X 4 MM, LEAD FREE, MO-220WGGD, QFN-24
文件頁(yè)數(shù): 9/26頁(yè)
文件大小: 244K
代理商: CP2110-F01-GM
CP2110
Rev. 1.1
17
7. Asynchronous Serial Data Bus (UART) Interface
The UART interface consists of the TX (transmit) and RX (receive) data signals as well as the optional RTS and
CTS flow control signals. The UART is programmable to support a variety of data formats and baud rates. The data
format and baud rate are set during device configuration on the PC. The data formats and baud rates available to
each interface are listed in Table 12.
The baud rate generator for the UART interface is very flexible and allows the user to request any baud rate in the
range from 300 bps to 1 Mbps. If the baud rate cannot be directly generated from the internal 24 MHz oscillator, the
device will choose the closest possible option. The actual baud rate is dictated by Equation 1 and Equation 2.
Equation 1. Clock Divider Calculation
Equation 2. Baud Rate Calculation
Most baud rates can be generated with an error of less than 1.0%. A general rule of thumb for the majority of UART
applications is to limit the baud rate error on both the transmitter and the receiver to no more than ±2%. The clock
divider value obtained in Equation 1 is rounded to the nearest integer, which may produce an error source. Another
error source will be the 24 MHz oscillator, which is accurate to ±0.25%. Knowing the actual and requested baud
rates, the total baud rate error can be found using Equation 3.
Equation 3. Baud Rate Error Calculation
The UART also supports the transmission of a line break. The length of time for a line break is programmable from
1 to 125 ms, or it can be set to transmit indefinitely until a stop command is sent from the application.
Table 12. Data Formats and Baud Rates
Data Bits
5, 6, 7, and 8
Stop Bits
1, 1.51, and 2
Parity Type
None, Even, Odd, Mark, Space
Baud Rate
300 bps to 1 Mbps2
Notes:
1. 1.5 stop bits only available when using 5 data bits.
2. Baud rates above 500,000 baud not supported with 5 or 6 data bits.
Clock Divider
24 MHz
2
Prescale
Requested Baud Rate
----------------------------------------------------------------------------------------------------
=
Prescale
4 if Requested Baud Rate
300 bps
=
Prescale
1 if Requested Baud Rate
300 bps
=
Actual Baud Rate
24 MHz
2
Prescale
Clock Divider
-----------------------------------------------------------------------------
=
Prescale
4 if Requested Baud Rate
300 bps
=
Prescale
1 if Requested Baud Rate
300 bps
=
Baud Rate Error (%)
100
1
Actual Baud Rate
Requested Baud Rate
-----------------------------------------------------------
0.25%
=
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