參數(shù)資料
型號(hào): CP2110-F01-GM
廠商: SILICON LABORATORIES
元件分類(lèi): 總線(xiàn)控制器
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, QCC24
封裝: 4 X 4 MM, LEAD FREE, MO-220WGGD, QFN-24
文件頁(yè)數(shù): 13/26頁(yè)
文件大小: 244K
代理商: CP2110-F01-GM
CP2110
20
Rev. 1.1
8.3. GPIO.3—RS-485 Transceiver Bus Control
GPIO.3 is configurable as an RS-485 bus transceiver control pin that is connected to the DE and RE inputs of the
transceiver. When configured for RS-485 mode, the pin is asserted during UART data transmission as well as line
break transmission. The RS-485 mode of GPIO.3 is active-high by default, but is also configurable for active-low
mode.
Figure 9. RS-485 Transceiver Typical Connection Diagram
8.4. GPIO.4-5—Transmit and Receive Toggle
GPIO.4 and GPIO.5 are configurable as Transmit Toggle and Receive Toggle pins. These pins are logic high when
a device is not transmitting or receiving data, and they toggle at a fixed rate as specified in Table 6 when data
transfer is in progress. Typically, these pins are connected to two LEDs to indicate data transfer.
Figure 10. Transmit and Receive Toggle Typical Connection Diagram
More information regarding the configuration and usage of these pins can be found in Section 9 as well as “AN144:
CP21xx Customization Guide” available on the Silicon Labs web site.
RS485
Transceiver
R
D
DE
RE
CP2110
TX
RX
GPIO.3 – RS485
CP2110
GPIO.4 – TX Toggle
GPIO.5 – RX Toggle
VIO
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