參數(shù)資料
型號(hào): CP2110-F01-GM
廠商: SILICON LABORATORIES
元件分類(lèi): 總線控制器
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, QCC24
封裝: 4 X 4 MM, LEAD FREE, MO-220WGGD, QFN-24
文件頁(yè)數(shù): 15/26頁(yè)
文件大?。?/td> 244K
代理商: CP2110-F01-GM
CP2110
22
Rev. 1.1
10. Voltage Regulator
The CP2110 includes an on-chip 5 to 3.45 V voltage regulator. This allows the CP2110 to be configured as either a
USB bus-powered device or a USB self-powered device. A typical connection diagram of the device in a bus-
powered application using the regulator is shown in Figure 11. When enabled, the voltage regulator output appears
on the VDD pin and can be used to power external devices. See Table 5 for the voltage regulator electrical
characteristics. If the regulator is used to provide VDD in a self-powered application, use the same connections
from Figure 11, but connect REGIN to an on-board 5 V supply, and disconnect it from the VBUS pin.
Figure 11. Typical Bus-Powered Connection Diagram
Note 3
Note 2
VBUS
D+
D-
GND
USB
Connector
Suspend
Signals
Standard
UART
and GPIO
Signals
CP2110
GPIO.0_CLK
GPIO.1_RTS
GPIO.2_CTS
GPIO.3_RS485
TX
RX
VPP
SUSPEND
GPIO.4_TXT
GPIO.5_RXT
GPIO.8
GPIO.9
GPIO.6
GPIO.7
VBUS
D+
D-
RST
VIO
4.7 k
Note 4
Note 1 : VIO can be connected directly to VDD or to a supply as low as 1.8 V to set the I/O interface
voltage. VIO is internally connected to VDD on -GM1 packages.
Note 2 : Avalanche transient voltage suppression diodes compatible with Full-speed USB should be
added at the connector for ESD protection. Use Littelfuse p/n SP0503BAHT or equivalent.
Note 3 : An external pull-up is not required, but can be added for noise immunity.
Note 4 : If programming the configuration ROM via USB, add a 4.7
F capacitor between VPP
and ground. During a programming operation, do not connect the VPP pin to other
circuitry, and ensure that VDD is at least 3.3 V.
4.7
F
Note 1
REGIN
VDD
GND
VIO
1
F
1-5
F
0.1
F
3.45 V Power
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