參數(shù)資料
型號(hào)： COP8SDR9IMT7
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： 8-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout
中文描述： 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDSO48
封裝： TSSOP-48
文件頁數(shù)： 14/80頁
文件大小： 972K
代理商： COP8SDR9IMT7
8.0 Electrical Characteristics
AC Electrical Characteristics (40C
≤
T
A
≤
+85C)
(Continued)
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
(Continued)
Parameter
Conditions
Min
1
1
1
1
Typ
Max
Units
t
C
t
C
Timer 1 Input High Time
Timer 1 Input Low Time
Timer 2, 3 Input High Time (Note 6)
Timer 2, 3 Input Low Time (Note 6)
Output Pulse Width
Timer 2, 3 Output High Time
Timer 2, 3 Output Low Time
USART Bit Time when using External
CKX
USART CKX Frequency when being
Driven by Internal Baud Rate Generator
Reset Pulse Width
t
C
= instruction cycle time.
Note 2:
Maximum rate of voltage change must be
<
0.5 V/ms.
Note 3:
Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180 out of phase with CKI, inputs connected to V
CC
and outputs driven low but not connected to a load.
Note 4:
The HALT mode will stop CKI from oscillating. Measurement of I
DD
HALT is done with device neither sourcing nor sinking current; with L. A. B, C, E, F, G0,
and G2–G5 programmed as low outputs and not driving a load; all D outputs programmed low and not driving a load; all inputs tied to V
CC
; A/D converter and clock
monitor and BOR disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register.
Note 5:
Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages
>
V
CC
and the pins will have sink current to V
CC
when
biased at voltages
>
V
CC
(the pins do not have source current when biased at a voltage below V
CC
). These two pins will not latch up. The voltage at the pins must
be limited to
<
14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD transients.
Note 6:
If timer is in high speed mode, the minimum time is 1 MCLK. If timer is not in high speed mode, the minimum time is 1 t
C
.
Note 7:
Absolute Maximum Ratings should not be exceeded.
Note 8:
V
CC
must be valid and stable before G6 is raised to a high voltage.
MCLK or t
C
MCLK or t
C
150
150
6 CKI
periods
ns
ns
μs
2
MHz
1
t
C
DC Electrical Characteristics (40C
≤
T
A
≤
+125C)
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Parameter
Conditions
Min
4.5
10
Typ
Max
5.5
50 x 10
6
0.1 V
CC
Units
V
ns
V
Operating Voltage
Power Supply Rise Time
Power Supply Ripple (Note 2)
Supply Current (Note 3)
High Speed Mode
CKI = 10 MHz
CKI = 3.33 MHz
Dual Clock Mode
CKI = 10 MHz, Low Speed OSC = 32 kHz
CKI = 3.33 MHz, Low Speed OSC = 32 kHz
Low Speed Mode
Low Speed OSC = 32 kHz
HALT Current with BOR Disabled (Note 4)
High Speed Mode
Dual Clock Mode
Peak-to-Peak
V
CC
= 5.5V, t
C
= 0.5 μs
V
CC
= 4.5V, t
C
= 1.5 μs
14.5
7
mA
mA
V
CC
= 5.5V, t
C
= 0.5 μs
V
CC
= 4.5V, t
C
= 1.5 μs
14.5
7
mA
mA
V
CC
= 5.5V
65
110
μA
V
CC
= 5.5V, CKI = 0 MHz
V
CC
= 5.5V, CKI = 0 MHz, Low
Speed OSC = 32 kHz
V
CC
= 5.5V, CKI = 0 MHz, Low
Speed OSC = 32 kHz
<
4
40
μA
<
9
50
μA
Low Speed Mode
<
9
50
μA
Idle Current (Note 3)
High Speed Mode
CKI = 10 MHz
V
CC
= 5.5V, t
C
= 0.5 μs
2.7
mA
C
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