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參數資料
| 型號： | CN8332EXF |
| 英文描述： | PCM Transceiver |
| 中文描述： | 收發(fā)器的PCM |
| 文件頁數： | 30/48頁 |
| 文件大小： | 434K |
| 代理商： | CN8332EXF |
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2.0 Functional Description
CN8331/CN8332/CN8333
2.3 Receiver
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2-12
Conexant
100604B
2.3.7 B3ZS/HDB3 Decoder With Bipolar Violation Detector
In the CN833x device, when ENDECDIS = 0 (encoder/decoder enabled), the
decoder takes the output from the clock recovery circuit and decodes the data
(HDB3 or B3ZS) into a single retimed NRZ data signal. The data signal is then
sent out of the CN833x over the RNRZ (RPOS) pin. Any detected Line Code
Violations (LCV) are sent out over the corresponding RLCV (RNEG) pin. The
RLCV pin is asserted for one symbol period at the time the violation appears on
the RX output pin (RNRZ).
The following shows data sequence criteria for LCV; violations are indicated
in bold text. A valid bipolar pulse is indicated by a B. A bipolar violation
(non-alternating positive or negative) pulse is indicated by a V
Excessive zeros: 0, 0, 0,
0
(HDB3) or 0, 0,
0
(B3ZS). These violations are
passed on as 0 data on the RNRZ pin.
Bipolar violation: B, 0,
V
(i.e., +1, 0,
+1
or -1, 0,
-1
for HDB3) B,
V
(B3ZS and HDB3). These violations are passed on as 1 data on the RNRZ
pin.
Coding violation: 0, 0,
V
(HDB3) or 0,
V
(B3ZS) with an even number of
Bs since the last valid 0 substitution V (follows coding rule). These
violations are passed on as 0 data on the RNRZ pin.
The even/odd counter (used to count the number of Bs between Vs) will count
a bipolar violation as a B. A coding violation or a valid 0 substitution resets the
counter.
When ENDECDIS = 1, the decoder is disabled, and the retimed slicer outputs
are sent out over RPOS (RNRZ) and RNEG (RLCV) pins. These outputs are then
decoded by the CN8340/CN8330 or other downstream device. Line code
violations are not detected in this mode of operation. The decoder is configurable
for either:
E3 mode using HDB3 coding (E3MODE = 1)
DS3/STS-1 mode using B3ZS coding (E3MODE = 0)
The receiver digital data outputs are centered on the rising edge of RCLK
(see
Section 2.8
).
2.3.8 Data Squelching
A counter in the receiver keeps track of the number of consecutive symbol
periods without a valid data pulse. When 128 or more 0s in a row are counted, the
receiver assumes that it has lost the signal and resets itself to try and regain the
signal. While the receiver is reacquiring the signal, the clock recovery block locks
to the reference clock and the data squelching is achieved by forcing the data bits
to zero. The data squelching is true in both NRZ and dual rail mode. When the
input signal has been properly amplified and equalized, the clock recovery PLL
will then switch to the incoming data.
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