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參數(shù)資料
| 型號： | CLC031VEC |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancilliary Data FIFOs |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | TQFP-64 |
| 文件頁數(shù)： | 21/31頁 |
| 文件大小： | 383K |
| 代理商： | CLC031VEC |
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Device Operation
(Continued)
reported via the
ANC Checksum Error
bit.
ANC Checksum
Error
is available as an output on the multifunction I/O port.
ANC 1 AND 2 (Addresses 05h and 06h)
The extraction of ancilliary data packets from video data into
the FIFO is controlled by the
ANC MASK[15:0]
and
ANC
ID[15:0]
bits in the control registers. The
ANC ID[7:0]
reg-
ister normally is set to a valid 8-bit code used for component
ancilliary data packet DID identification as specified in
SMPTE 291M-1998. Similarly,
ANC ID[15:8]
normally is set
to a valid 8-bit code used for component ancilliary data
packet SDID/DBN identification.
ANC 3 AND 4 (Addresses 07h and 08h)
The
ANC MASK[7:0]
is an 8-bit word that can be used to
selectively control extraction of packets with specific DIDs
(or DID ranges) into the FIFO. When the
ANC MASK[7:0]
is
set to FFh, packets with any DID can be extracted into the
FIFO. When any bit or bits of the
ANC MASK[7:0]
are set to
a logic-1, the corresponding bit or bits of the
ANC ID[7:0]
are
a don’t-care when matching DIDs of packets being ex-
tracted. When the
ANC MASK[7:0]
is set to 00h, the ANC
DID of incoming packets must match exactly, bit-for-bit the
ANC ID[7:0]
set in the control register for the packets to be
extracted into the FIFO. The initial value of the
ANC
MASK[7:0]
is FFh and the
ANC ID[7:0]
is 00h.
Similarly,
ANC MASK[15:8]
is an 8-bit word that can be
used to selectively control extraction of packets with specific
SDID/DBN (or SDID/DBN ranges) into the FIFO. Operation
and use of these bits is the same as for
ANC MASK[7:0]
previously discussed.
ANC 5 (Address 17h)
The
FIFO EXTRACT ENABLE
bit in the control registers
enables the device to extract or copy ancilliary data from the
video data stream and place it in the ANC FIFO. From there
data may be output via the parallel ancilliary port. Data
extraction is enabled when this bit is set to a logic-1. This bit
can be used to delay automatic extraction and therefore the
output of parallel ancilliary data.
FIFO EXTRACT ENABLE
should be asserted during an SAV or EAV to avoid timing
problems with ancilliary data extraction.Access to data in the
FIFO is controlled by the
RD/WR
,
ANC/CTRL
and
A
CLK
control signals.
To conserve power when the ancilliary data function is not
being used, the internal Ancilliary Data FIFO clock is dis-
abled. This clock must be enabled before ancilliary data may
be replicated into the FIFO for output.
FIFO CLOCK EN-
ABLE
, bit-6 of the
ANC 5
register (address 17h), when set,
enables this clock to propagate to the FIFO. The default
condition of
FIFO CLOCK ENABLE
is OFF. After enabling
the internal FIFO clock by turning this bit ON,
A
CLK
must be
toggled three (3) times to propagate the enable to the clock
tree.
A
CLK
should remain running at all times when the ANC
FIFO is in use. Otherwise, message tracking and related
functions will not operate correctly.
The CLC031 can keep track of up to 8 ANC data packets in
the ANC FIFO. Incoming packet length versus available
space in the FIFO is also tracked. The
MSG TRACK
bit in
the control registers, when set, enables tracking of packets
in the FIFO. Other functions for control of packet traffic in the
FIFO are
FIFO FLUSH STAT
and
MSG FLUSH STAT
. If the
user wishes to handle more than 8 messages, the
MSG
TRACK
bit should be turned off (reset). The operation
FIFO
FLUSH STAT
will no longer work and the function
FULL
MSG AVAILABLE
will no longer be a reliable indicator that
messages are available in the FIFO. The user may still
effectively use the FIFO by monitoring the states of
ANC
FIFO EMPTY
,
ANC FIFO FULL
,
ANC FIFO 90%FULL
and
ANC FIFO OVERRUN
.
Setting the
FIFO FLUSH STAT
bit to a logic-1 flushes the
FIFO.
FIFO FLUSH STAT
may not be set while the FIFO is
being accessed (Read or Write).
FIFO FLUSH STAT
is
automatically reset after this operation is complete.
When
MSG FLUSH STAT
is set to a logic-1, the oldest
message packet in the FIFO is flushed when data is not
being written to the FIFO.
MSG FLUSH STAT
is automati-
cally reset after this operation is complete.
The
FULL MSG AVAILABLE
bit in the control registers,
when set, notifies the host system that complete packets
reside in the Ancilliary Data FIFO. When this bit is not set,
the messages in the FIFO are incomplete or partial. This
function is not affected by
MSG TRACK
. The
FULL MSG
AVAILABLE
function is most useful when mapped to the
multifunction I/O port as an output.
ANC 6 (Address 18h)
The
ANC FIFO 90% FULL
flag bit indicates when the ANC
FIFO is 90% full. This bit may be mapped to the multi-
function I/O port. The purpose of this flag is to provide a
signal which gives the host system time to begin reading
from the FIFO before it has the chance to overflow. This was
done because it is virtually impossible to monitor the FIFO
FULL flag and begin extracting from the FIFO before an
overrun condition occurs.
The
SHORT MSG DETECT
flag bit indicates when short
ANC messages have been detected. i.e. An ANC header
was detected before the last full message was recovered.
This bit may be mapped to the multi-function I/O port.
The
ANC PARITY MASK
bit when set disables parity check-
ing for DID and SDID words in the ANC data packet. When
reset, parity checking is enabled; and, if a parity error occurs,
the packet will not be extracted.
The
VANC
bit, when set, enables extraction of ANC data
present in the vertical blanking interval (both active video
and horizontal blanking portions of the line).
FORMAT 0 (Address 0Bh)
The CLC031 may be set to process a single video format by
writing the appropriate data into the
FORMAT 0
register. The
Format Set[4:0]
bits confine the CLC031 to recognize and
process only one of the fourteen specified type of SD or HD
formats defined by a particular SMPTE specification. The
Format Set[4:0]
bits may not be used to confine device
operation to a range of standards. The available formats and
codes are detailed in
Table 4
. Generally speaking, the
For-
mat Set[4:0]
codes indicate or group the formats as follows:
Format Set[4]
is set for the HD data formats, reset for SD
data formats.
Format Set[3]
is set for PAL data formats (with
the exception of the SMPTE 274M 24-frame progressive
format), reset for NTSC data formats.
Format Set[2:0]
fur-
ther sub-divide the standards as given in the table.
C
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21
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