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參數(shù)資料
| 型號： | CLC021AVGZ-5.0 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SMPTE 259M Digital Video Serializer with EDH Generation and Insertion |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP44 |
| 封裝： | MERTIC, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 5/18頁 |
| 文件大?。?/td> | 428K |
| 代理商： | CLC021AVGZ-5.0 |
DC Electrical Characteristics—CLC021AVGZ-3.3
(Continued)
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3).
Symbol
V
OH
Parameter
Conditions
Reference
Min
Typ
Max
Units
CMOS Output Voltage
High Level
CMOS Output Voltage
Low Level
Serial Driver Output
Voltage
I
OH
= 8 mA
All CMOS
Outputs
2.4
3.0
V
DD
V
V
OL
I
OL
= +8 mA
0.0
0.3
V
SS
+ 0.5V
V
V
SDO
R
L
= 75
1%,
R
REF
= 1.69 k
1%,
Figure 2
R
L
= 75
1%,
R
REF
= 1.69 k
1%,
P
CLK
= 27 MHz, NTSC
Colour Bar Pattern,
Figure 2
SDO, SDO
720
800
880
mV
P-P
I
DD
Power Supply Current,
Total
33
55
mA
AC Electrical Characteristics—CLC021AVGZ-5.0
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3).
Symbol
BR
SDO
Parameter
Conditions
Reference
SDO, SDO
Min
100
Typ
Max
400
Units
Mbps
Serial Data Rate
Reference Clock
Input Frequency
Reference Clock Duty
Cycle
Rise Time, Fall Time
Serial Output Jitter
Serial Output Jitter
Rise Time, Fall Time
Output Overshoot
Lock Time
Setup Time
Hold Time
Output Inductance
Output Resistance
(Note 5)
F
P
CLK
P
CLK
10
40
MHz
P
CLK
45
50
55
%
t
r
, t
f
t
j
t
jit
t
r
, t
f
D
N
, P
CLK
1.0
1.5
220
100
800
1
75
2
2
6
25k
3.0
ns
270 Mbps,
Figure 2
, (Note 6)
(Notes 4, 5)
20%–80%, (Notes 4, 5)
(Note 4)
(Notes 5, 7)
Figure 3
(Note 4)
Figure 3
(Note 4)
(Note 4)
(Note 4)
SDO, SDO
ps
P-P
ps
P-P
ps
%
μs
ns
ns
nH
200
1500
500
t
LOCK
t
SU
t
HLD
L
GEN
R
GEN
D
N
to P
CLK
D
N
from P
CLK
3
3
SDO, SDO
AC Electrical Characteristics—CLC021AVGZ-3.3
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3).
Symbol
BR
SDO
Parameter
Conditions
Reference
SDO, SDO
Min
100
Typ
Max
400
Units
Mbps
Serial Data Rate
Reference Clock
Input Frequency
Reference Clock Duty
Cycle
Rise Time, Fall Time
Serial Output Jitter
Serial Output Jitter
Rise Time, Fall Time
Output Overshoot
Lock Time
Setup Time
Hold Time
(Note 5)
F
P
CLK
P
CLK
10
40
MHz
P
CLK
45
50
55
%
t
r
, t
f
t
j
t
jit
t
r
, t
f
D
N
, P
CLK
1.0
1.5
220
100
800
1
75
2
2
3.0
ns
270 Mbps,
Figure 2
, (Note 6)
(Notes 4, 5)
20%–80%, (Notes 4, 5)
(Note 4)
(Notes 5, 7)
Figure 3
(Note 4)
Figure 3
(Note 4)
SDO, SDO
ps
P-P
ps
P-P
ps
%
μs
ns
ns
200
1500
500
t
LOCK
t
SU
t
HLD
D
N
to P
CLK
D
N
from P
CLK
4
4
C
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