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參數(shù)資料
| 型號： | CLC021AVGZ-5.0 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SMPTE 259M Digital Video Serializer with EDH Generation and Insertion |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP44 |
| 封裝： | MERTIC, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 428K |
| 代理商： | CLC021AVGZ-5.0 |
Application Information
A typical application circuit for the CLC021 is shown in
Figure 8
. This circuit demonstrates the capabilities of the
CLC021 and allows its evaluation in a variety of configura-
tions. Assembled demonstration boards with more compre-
hensive evaluation options are available, part number
SD021-5EVK (5V device) or SD021-3EVK (3.3V device).
The boards may be ordered through any of National’s sales
offices. Complete circuit board layouts and schematics in-
cluding Gerber photoplot files, for the demonstration boards
are available on National’s WEB site in the application infor-
mation for this device. For latest information, please see:
www.national.com/appinfo/interface.
APPLICATION CIRCUIT
The SD021EVK application circuit boards,
Figure 9
, can
accommodate different input and output drive and loading
options. Pin headers are provided for input and control I/O
signal access. Install the appropriate value resistor packs,
220
at RP1 and RP3 and 330
at RP2 and RP4, for TTL
cabled interfaces before applying input signals. Install 51
resistor packs at RP2 and RP4 for signal sources requiring
such loading. Remove any resistor packs at RP1 and RP3
when using 50
source loading.
The board’s outputs may be DC interfaced to PECLinputs by
first installing 124
resistors at R1B and R2B, changing R1A
and R2A to 187
and replacing C1 and C2 with short
circuits. The PECL inputs should be directly connected to J1
and J2 without cabling. If 75
cabling is used to connect the
CLC021 to the PECL inputs, the voltage dividers used on the
CLC021 outputs must be removed and re-installed on the
circuit board where the PECL device is mounted. This will
provide correct termination for the cable and biasing for both
the CLC021’s outputs and the PECL inputs. It is most impor-
tant to note that a 75
or equivalent DC loading (measured
with respect to the negative supply rail) must always be
installed at both of the CLC021’s SDO outputs to obtain
proper signal levels from device. When using 75
Thevenin-
equivalent load circuits, the DC bias applied to the SDO
outputs should not exceed +3V (+1.3V for CLC021AVGZ-
3.3) with respect to the negative supply rail. Serial output
levels should be reduced to 400 mV
by changing R
to
3.4 k
. This may be done by removing the Output Level
shorting jumper on the post header.
10136808
FIGURE 8. Typical Application Circuit
C
www.national.com
14
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| CLC021 | SMPTE 259M Digital Video Serializer with EDH Generation/Insertion(SMPTE 259M數(shù)字視頻串行器帶EDH發(fā)生/插入) |
| CLC030VEC | SMPTE 292M/259M Digital Video Serializer with Video and Ancilliary Data FIFOs and Integrated Cable Driver |
| CLC030 | SMPTE 292M/259M Digital Video Serializer with Video and Ancilliary Data FIFOs and Integrated Cable Driver |
| CLC031A | SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancillary Data FIFOs |
| CLC031AVEC | SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancillary Data FIFOs |
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