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參數(shù)資料
| 型號： | CLC021AVGZ-5.0 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SMPTE 259M Digital Video Serializer with EDH Generation and Insertion |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP44 |
| 封裝： | MERTIC, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 13/18頁 |
| 文件大小： | 428K |
| 代理商： | CLC021AVGZ-5.0 |
Pin Descriptions
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Name
Description
Manual Reset Input (High True)
NRZ-to-NRZI Conversion Control (NRZ=High, NRZI=Low)
Test Out (BIST Pass/Fail Indicator)
Negative Power Supply Input (Digital Logic)
Negative Power Supply Input (Digital Logic)
Positive Power Supply Input (Digital Logic)
Positive Power Supply Input (Digital Logic)
Force Insertion of New EDH and Flags in Serial Output Data (High True)
EDH Enable Input (Low True)
SMPTE/non-SMPTE Mode Select Input (SMPTE Mode=Low)
No Connect
Parallel Data Input (Internal Pull-Down to V
SS
)
Parallel Data Input (Internal Pull-Down to V
SS
)
Parallel Data Input (Internal Pull-Down to V
SS
)
Parallel Data Input (Internal Pull-Down to V
SS
)
Parallel Data Input (Internal Pull-Down to V
SS
)
Parallel Data Input (Internal Pull-Down to V
SS
)
Parallel Data Input (Internal Pull-Down to V
SS
)
Parallel Data Input (Internal Pull-Down to V
SS
)
Parallel Data Input (Internal Pull-Down to V
SS
)
Parallel Data Input (Internal Pull-Down to V
SS
)
Parallel Clock Input (Internal Pull-Down to V
SS
)
H-Bit Output (Component); Line-Field ID (Composite)
V-Bit Output (Component); Line-Field ID (Composite)
F-Bit Output (Component); Line-Field ID (Composite)
Lock Detector Output (High True)
Negative Power Supply Input (PLL Supply)
Positive Power Supply Input (PLL Supply)
TPG Enable (High True)
Negative Power Supply Input (PLL Digital Supply)
Negative Power Supply Input (PLL Digital Supply)
Positive Power Supply Input (PLL Digital Supply)
Positive Power Supply Input (PLL Digital Supply)
No Connect
Output Level Reference Resistor (1.69 k
, 1% Nominal Value)
Positive Power Supply Input (PLL Digital Supply)
Negative Power Supply Input (Output Driver)
Serial Data True Output
Serial Data Complement Output
Positive Power Supply Input (Output Driver)
Parallel Data Sync Detection Enable Input (Low True)
New Sync Position Output
Ancilliary Data Header Flag Output
NTSC/PAL Mode Indicator Output (PAL=High, NTSC=Low)
Reset
NRZ-NRZI
Test Out
V
SS
V
SS
V
DD
V
DD
EDH Force
EDH Enable
SMPTE Mode
N/C
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
P
CLK
H/Line-Field b0 (LSB)
V/Line-Field b1
F/Line-Field b2 (MSB)
Lock Detect
V
SSO
V
DDO
TPG Enable
V
SSOD
V
SSOD
V
DDOD
V
DDOD
N/C
R
REF
V
DDOD
V
SSSD
SDO
SDO
V
DDSD
Sync Detect Enable
NSP
ANC
NTSC/PAL
Note:
All CMOS/TTL inputs have internal pull-down devices.
C
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| CLC021 | SMPTE 259M Digital Video Serializer with EDH Generation/Insertion(SMPTE 259M數(shù)字視頻串行器帶EDH發(fā)生/插入) |
| CLC030VEC | SMPTE 292M/259M Digital Video Serializer with Video and Ancilliary Data FIFOs and Integrated Cable Driver |
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| CLC031A | SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancillary Data FIFOs |
| CLC031AVEC | SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancillary Data FIFOs |
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