參數(shù)資料
型號(hào)： CLC021AVGZ-5.0
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 消費(fèi)家電
英文描述： SMPTE 259M Digital Video Serializer with EDH Generation and Insertion
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP44
封裝： MERTIC, PLASTIC, QFP-44
文件頁(yè)數(shù)： 16/18頁(yè)
文件大小： 428K
代理商： CLC021AVGZ-5.0
Application Information
(Continued)
The jitter test setup used to obtain values quoted in the data
sheet consists of:
National Semiconductor SD021-5EVK (SD021-3EVK),
CLC021 evaluation kit
Tektronix TG2000 signal generation platform with DVG1
option
Tektronix VM700T Option 1S Video Measurement Set
Tektronix TDS 794D, Option C2 oscilloscope
Tektronix P6339A passive probe
75
coaxial cable, 3 ft., Belden 8281 or RG59 (2 re-
quired)
ECL-to-TTL/CMOS
level
Figure 11
).
Apply the black-burst reference clock from the TG2000 sig-
nal generator’s BG1 module 27 MHz clock output to the level
converter input. The clock amplitude converter schematic is
shown in
Figure 11
. Adjust the input bias control to give a
50% duty cycle output as measured on the oscilloscope/
probe system. Connect the level translator to the SD021EVK
board, connector P1, P
CLK
pins (the outer-most row of pins
converter/amplifier,
(see
is ground). Configure the SD021EVK to operate in the NTSC
colour bars, BIST mode. Configure the VM700T to make the
jitter measurement in the jitter FFT mode at the frame rate
with 1 kHz filter bandwidth and Hanning window. Configure
the setup as shown in
Figure 10
. Switch the test equipment
on (from standby mode) and allow all equipment tempera-
tures stabilize per manufacturer’s recommendation. Mea-
sure the jitter value after allowing the instrument’s reading to
stabilize (about 1 minute). Consult the VM700T Video Mea-
surement Set Option 1S Serial Digital Measurements User
Manual (document number 071-0074-00) for details of
equipment operation.
The VM700T measurement system’s jitter floor specification
at 270 Mbps is given as 200 ps
±
20% (100 ps
±
5% typical)
of actual components from 50 Hz to 1 MHz and 200 ps
+60%, -30% of actual components from 1 MHz to 10 MHz.
To obtain the actual residual jitter of the CLC021, a root-sum-
square adjustment of the jitter reading must be made to
compensate for the measurement system’s jitter floor speci-
fication. For example, if the jitter reading is 250 ps, the
CLC021 residual jitter is the square root of (250
2
200
2
) =
150 ps. The accuracy limits of the reading as given above
apply.
10136810
FIGURE 10. Jitter Test Circuit
10136813
FIGURE 11. ECL-to-TTL/CMOS Level Converter/Amplifer
C
www.national.com
16
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