參數(shù)資料
型號： CDCE913_1
廠商： Texas Instruments, Inc.
英文描述： Programmable 1-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V, and 3.3-V Outputs
中文描述： 可編程1 - PLL頻率石英振蕩器時鐘合成器的1.8 V，2.5 V和3.3 V輸出
文件頁數(shù)： 6/23頁
文件大?。?/td> 428K
代理商： CDCE913_1
www.ti.com
DEVICE CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
CDCE913
CDCEL913
SCAS849A–JUNE 2007–REVISED AUGUST 2007
PARAMETER
TEST CONDITIONS
MIN
TYP
(1)
MAX
UNIT
OVERALL PARAMETER
All outputs off, f
CLK
= 27 MHz,
f
VCO
= 135 MHz;
f
OUT
= 27 MHz
All PLLS on
11
I
DD
Supply current (see
Figure 3
)
mA
9
Per PLL
V
DDOUT
= 3.3 V
V
DDOUT
= 1.8 V
1.3
No load, all outputs on,
f
OUT
= 27 MHz
I
DD(OUT)
Supply current (see
Figure 4
and
Figure 5
)
mA
0.7
Power-down current. Every circuit powered
down except SDA/SCL
I
DD(PD)
f
IN
= 0 MHz,
V
DD
= 1.9 V
30
μ
A
Supply voltage Vdd threshold for power-up
control circuit
V
(PUC)
0.85
1.45
V
f
VCO
VCO frequency range of PLL
80
230
MHz
V
DDOUT
= 3.3 V
V
DDOUT
= 1.8 V
230
f
OUT
LVCMOS output frequency
MHz
230
LVCMOS PARAMETER
V
IK
I
I
I
IH
I
IL
LVCMOS input voltage
V
DD
= 1.7 V; I
I
= –18 mA
V
I
= 0 V or V
DD
; V
DD
= 1.9 V
V
I
= V
DD
; V
DD
= 1.9 V
V
I
= 0 V; V
DD
= 1.9 V
V
IClk
= 0 V or V
DD
V
IXout
= 0 V or V
DD
V
IS
= 0 V or V
DD
–1.2
V
LVCMOS Input current
±5
μ
A
LVCMOS Input current for S0/S1/S2
5
μ
A
LVCMOS Input current for S0/S1/S2
–4
μ
A
Input capacitance at Xin/Clk
6
C
I
Input capacitance at Xout
2
pF
Input capacitance at S0/S1/S2
3
CDCE913 - LVCMOS PARAMETER FOR V
DDOUT
= 3.3 V – MODE
V
DDOUT
= 3 V, I
OH
= –0.1 mA
V
DDOUT
= 3 V, I
OH
= –8 mA
V
DDOUT
= 3 V, I
OH
= –12 mA
V
DDOUT
= 3 V, I
OL
= 0.1 mA
V
DDOUT
= 3 V, I
OL
= 8 mA
V
DDOUT
= 3 V, I
OL
= 12 mA
PLL bypass
2.9
V
OH
LVCMOS high-level output voltage
2.4
V
2.2
0.1
V
OL
LVCMOS low-level output voltage
0.5
V
0.8
t
PLH
, t
PHL
t
r
/t
f
t
jit(cc)
t
jit(per)
t
sk(o)
odc
Propagation delay
3.2
ns
Rise and fall time
Cycle-to-cycle jitter
(2) (3)
Peak-to-peak period jitter
(3)
Output skew
(4)
, See
Table 2
Output duty cycle
(5)
V
DDOUT
= 3.3 V (20%–80%)
1 PLL switching, Y2-to-Y3
0.6
ns
50
70
ps
1 PLL switching, Y2-to-Y3
60
100
ps
f
OUT
= 50 MHz; Y1-to-Y3
f
VCO
= 100 MHz; Pdiv = 1
60
ps
45%
55%
CDCE913 – LVCMOS PARAMETER for V
DDOUT
= 2.5 V – Mode
V
DDOUT
= 2.3 V, I
OH
= –0.1 mA
V
DDOUT
= 2.3 V, I
OH
= –6 mA
V
DDOUT
= 2.3 V, I
OH
= –10 mA
V
DDOUT
= 2.3 V, I
OL
= 0.1 mA
V
DDOUT
= 2.3 V, I
OL
= 6 mA
V
DDOUT
= 2.3 V, I
OL
= 10 mA
PLL bypass
2.2
V
OH
LVCMOS high-level output voltage
1.7
V
1.6
0.1
V
OL
LVCMOS low-level output voltage
0.5
V
0.7
t
PLH
, t
PHL
t
r
/t
f
t
jit(cc)
t
jit(per)
t
sk(o)
odc
Propagation delay
3.6
ns
Rise and fall time
Cycle-to-cycle jitter
(2) (3)
Peak-to-peak period jitter
(3)
Output skew
(4)
, See
Table 2
Output duty cycle
(5)
V
DDOUT
= 2.5 V (20%–80%)
1 PLL switching, Y2-to-Y3
0.8
ns
50
70
ps
1 PLL switching, Y2-to-Y3
60
100
ps
f
OUT
= 50 MHz; Y1-to-Y3
f
VCO
= 100 MHz; Pdiv = 1
60
ps
45%
55%
(1)
(2)
(3)
(4)
(5)
All typical values are at respective nominal V
DD
.
10000 cycles.
Jitter depends on configuration. Jitter data is for input frequency = 27 MHz, f
= 108 MHz, f
= 27 MHz (measured at Y2).
The tsk(o) specification is only valid for equal loading of each bank of outputs, and the outputs are generated from the same divider.
odc depends on output rise and fall time (t
r
/t
f
); data sampled on rising edge (tr)
6
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Copyright 2007, Texas Instruments Incorporated
Product Folder Link(s):
CDCE913 CDCEL913
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