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參數(shù)資料
| 型號(hào)： | CDC9161 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PC Motherboard Clock Sythesizer/Drivers with SDRAM Clock Support(PC母板時(shí)鐘合成器/驅(qū)動(dòng)器(三態(tài)輸出)) |
| 中文描述： | 電腦主板時(shí)鐘Sythesizer /支持與SDRAM時(shí)鐘驅(qū)動(dòng)器（電腦母板時(shí)鐘合成器/驅(qū)動(dòng)器（三態(tài)輸出）） |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 212K |
| 代理商： | CDC9161 |
CDC9161
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS547B – NOVEMBER 1995 – REVISED JUNE 1996
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
switching characteristics (see Figures 1, 2, and 3)
PARAMETER
FROM
(INPUT)
TO
60 MHz
MIN
66 MHz
MIN
UNIT
(OUTPUT)
MAX
MAX
tc
tp(H)
tp(L)
tr
tf
Jitter
Duty cycle
tskew
tc
tp(H)
tp(L)
tr
tf
Jitter
Duty cycle
tskew
thpoffset
HCLKn
16.7
15
ns
HCLKn
6.0
5.2
ns
HCLKn
5.8
5.0
ns
HCLKn
0.4
1.6
0.4
1.6
ns
HCLKn
0.4
1.6
0.4
1.6
ps
HCLKn
±
250
±
250
ps
HCLKn
45%
55%
45%
55%
HCLKn
250
250
ps
PCKLn
33.3
30
ps
PCKLn
13.3
12
ns
PCKLn
13.3
12
ps
PCKLn
0.5
2.0
0.5
2.0
ns
PCKLn
0.5
2.0
0.5
2.0
ns
PCKLn
±
350
±
350
ps
PCKLn
45%
55%
45%
55%
PCKLn
500
500
ps
HCLKn
PCLKn
1
4
1
4
ns
Clock enable latency
PCLK_EN
PCLKn
↑
1
4
1
4
HCLK
cycles
HCLK_EN
HCLKn
↑
1
4
1
4
Specifications are applicable only after the PLL stabilization time has elapsed.
Rise and fall times are characterized using the load circuits shown in Figure 1.
P
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