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參數(shù)資料
| 型號： | CDC9161 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PC Motherboard Clock Sythesizer/Drivers with SDRAM Clock Support(PC母板時鐘合成器/驅(qū)動器(三態(tài)輸出)) |
| 中文描述： | 電腦主板時鐘Sythesizer /支持與SDRAM時鐘驅(qū)動器（電腦母板時鐘合成器/驅(qū)動器（三態(tài)輸出）） |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 212K |
| 代理商： | CDC9161 |
CDC9161
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS547B – NOVEMBER 1995 – REVISED JUNE 1996
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
MIN
MAX
UNIT
VCC
VCCO3
VCCO2
VIH3
VIL3
IOH
IOL
TA
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
3.3-V core supply voltage
3.135
3.465
V
3.3-V I/O supply voltage
3.135
3.465
V
2.5-V I/O supply voltage
2.375
2.9
V
High-level input voltage
2.0
VCCO3+0.3
V
Low-level input voltage
–0.3
0.8
V
High-level output current
–12
mA
Low-level output current
12
mA
°
C
Operating free-air temperature
0
70
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
VIK
VOH3
VOL3
VOH2
VOL2
II
IOZ
VCC = 3.135 V,
VCC = 3.135 V,
VCC = 3.135 V,
VCC = 2.375 V
VCC = 2.375 V
VCC = 3.465 V,
VCC = 3.465 V,
II = –18 mA
IOH = –1 mA
IOL = 1 mA
IOH = –1 mA
IOL = 1 mA
VI = VCC or GND
VO = 3.135 V or 0
–1.2
V
2.4
V
0.4
V
2
V
0.4
V
μ
A
μ
A
–5
5
ICC
VCC = 3.465 V,
VI = VCC or GND
3 465 V
IO = 0,
Outputs high
Outputs low
mA
Outputs disabled
Ci
Co
Lpin
Cpd
5
pF
6
pF
7
nH
VI = 3.135 V or 0
pF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figure 4)
MIN
MAX
UNIT
S bili
Stabilization time
After change to SEL0 or SEL1
After PWR_DWN
↑
After power up
3
3
3
ms
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at XIN.
P
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