參數(shù)資料
型號(hào): CDC9162
廠商: Texas Instruments, Inc.
英文描述: PC Motherboard Clock Sythesizer/Drivers with SDRAM Clock Support(PC母板時(shí)鐘合成器/驅(qū)動(dòng)器(三態(tài)輸出))
中文描述: 電腦主板時(shí)鐘Sythesizer /支持與SDRAM時(shí)鐘驅(qū)動(dòng)器(電腦母板時(shí)鐘合成器/驅(qū)動(dòng)器(三態(tài)輸出))
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文件大?。?/td> 211K
代理商: CDC9162
CDC9162
PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER
WITH 3-STATE OUTPUTS
SCAS573 – JUNE 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
P6 Microprocessor Clock Generation With
Mixed 2.5-V and 3.3-V Signaling
Four 2.5-V CPU Clock Outputs With
Programmable Frequency (60 MHz and
66 MHz)
2.5-V IOAPIC Clock Output
Eight 3.3-V PCI Clock Outputs
Two 3.3-V 48-MHz Serial Bus Clocks
3.3-V 24-MHz Floppy Controller Clock
Three 3.3-V 14.318-MHz Reference Clocks
All Output Clock Frequencies Derived From
a Single 14.31818-MHz Crystal Input
Internal Loop Filters for Phase-Lock Loops
(PLLs)
Power-Down and Test-Mode Support
Packaged in Plastic 300-mil Shrink
Small-Outline Package
description
The CDC9162 is an integrated clock synthesizer
and driver specifically designed for use with
microprocessors manufactured by Intel. The
CDC9162 generates the necessary clock signals
for a high-performance PC motherboard and
provides both 2.5-V and 3.3-V signaling to support
both processor/chipset clocks and PCI clocks.
The four host clock (HCLKn) outputs are programmable to 60 MHz or 66 MHz via the SEL control inputs. The
eight PCI clock (PCLKn) outputs are one-half the HCLK frequency, and are offset 1 ns to 4 ns from the rising
edge of the host clock. In addition, the CDC9162 generates two copies of a 48-MHz bus clock (SBCLK), a
24-MHz floppy controller clock (FCCLK), three copies of the 14.318-MHz reference clock (REFn), and a 2.5-V
IOAPIC clock at 14.318 MHz. All output frequencies are generated from a 14.31818-MHz crystal input.
A test clock can be driven over the XIN input in the test mode. The oscillator and PLLs are bypassed when
operating in the test mode.
PLLs are used to generate the host clock and serial bus clock frequencies. On-chip loop filters and internal
feedback eliminate the need for external components. The PCI clock frequency is derived from the base host
clock frequency; FCCLK is derived from the serial bus clock frequency.
The host and PCI clock outputs provide low-skew/low-jitter clock signals for reliable clock operation. All outputs
are 3 state and are disabled via the SEL inputs.
Copyright
1996, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DL PACKAGE
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REF1
REF0
GND
XIN
XOUT
PCLK_EN
V
CCO3
PCLK0
PCLK1
GND
PCLK2
PCLK3
PCLK4
PCLK5
V
CCO3
PCLK6
PCLK7
GND
(reserved)
(reserved)
V
CC
SBCLK0
SBCLK1
GND
V
CC
REF2
V
CCO2
IOAPIC
GND
GND
HCLK0
HCLK1
V
CCO2
HCLK2
HCLK3
GND
(reserved)
(reserved)
V
CC
FCCLK
GND
(reserved)
GND
HCLK_EN
PWR_DN
SEL0
SEL1
V
CC
P
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