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參數(shù)資料
| 型號(hào)： | CDC2587 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Octal Divided -by-2 Circuit/Clock Driver(3.3V鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器(三態(tài)輸出)) |
| 中文描述： | 八路分裂的× 2電路/時(shí)鐘驅(qū)動(dòng)器（3.3鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器（三態(tài)輸出）） |
| 文件頁(yè)數(shù)： | 7/8頁(yè) |
| 文件大?。?/td> | 163K |
| 代理商： | CDC2587 |
CDC2587
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS560B – DECEMBER 1995 – REVISED JULY 1996
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
3 V
0 V
1.5 V
1.5 V
tw
Input
VOLTAGE WAVEFORMS
PULSE DURATION
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tphase error
1.5 V
1.5 V
3 V
0 V
1.5 V
VOH
VOL
CLK
0.8 V
2 V
tr
tf
0.8 V
2 V
From Output
Under Test
CL = 30 pF
(see Note A)
500
FBIN
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
≤
150 MHz, ZO = 50
, tr
≤
2.5 ns, tf
≤
2.5 ns.
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
LOAD CIRCUIT
From Output
CL = 30 pF
(see Note A)
25
Measurement Point
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tphase error
FBIN
1.5 V
1.9 V
1.1 V
VOH
VOL
CLK
VTT
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
≤
150 MHz, ZO = 50
, tr
≤
2.5 ns, tf
≤
2.5 ns.
C. The outputs are measured one at a time with one transition per measurement.
D. VTT = VREF = VCC
×
0.4
1.5 V
1.5 V
Figure 2. Load Circuit and Voltage Waveforms for SSTL_3 Class 1
P
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