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參數(shù)資料
| 型號(hào)： | CDC2587 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Octal Divided -by-2 Circuit/Clock Driver(3.3V鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器(三態(tài)輸出)) |
| 中文描述： | 八路分裂的× 2電路/時(shí)鐘驅(qū)動(dòng)器（3.3鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器（三態(tài)輸出）） |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大?。?/td> | 163K |
| 代理商： | CDC2587 |
CDC2587
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS560B – DECEMBER 1995 – REVISED JULY 1996
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
The output-enable (OE) input provides control for the Y output banks. When OE is high, the outputs are in a
high-impedance state. When OE is low, the outputs switch in accordance with the select inputs. RESET provides
a master reset for the CDC2587 counter circuitry. This allows the outputs to be reset to a known state. TEST
provides a bypass of the integrated PLL and divider circuitry. When TEST is high, CLKIN bypasses the PLL and
is buffered directly to the outputs.
The loop filter components of the PLL are integrated on the CDC2587. This reduces the need for external loop
components and provides an easily implemented PLL circuit. FBOUT should be connected to the feedback
input (FBIN) for normal operation of the PLL.
The voltage-controlled oscillator (VCO) of the integrated PLL has an operating range of 100 MHz to 300 MHz.
The VCO is designed to operate at two to twelve times the CLKIN frequency. This allows the CDC2587 to
achieve output frequencies from 16.67 MHz to 150 MHz, with a duty cycle of 50%
5% ensured.
Independent analog V
CC
(AV
CC
) and ground (AGND) connections are provided for VCO stability.
CLKIN and FBIN can be configured to switch at SSTL_3 input levels by connecting V
REF
to a nominal reference
voltage of 1.5 V. If V
REF
is strapped to GND, CLKIN and FBIN switch at normal TTL input thresholds.
Because the CDC2587 is based on PLL technology, it requires a stabilization time to achieve phase lock of the
feedback signal to the CLKIN reference. This stabilization time is required following power up and application
of a fixed-frequency, fixed-phase signal at CLKIN. In addition, a stabilization time may be required, following
changes to the SELn inputs, TEST inputs, or a change in frequency of CLKIN.
FUNCTION TABLE
(PLL enabled)
INPUTS
OUTPUTS
OE
SEL3
SEL2
SEL1
SEL0
FINmin
Note 1
FINmax
Note 1
FBOUT
1Y(0:3)
2Y(0:3)
3Y(0:3)
4Y(0:3)
H
X
X
X
X
Note 1
Hi Z
Hi Z
Hi Z
Hi Z
L
L
L
L
L
50 MHz
150 MHz
VCO/2
1X
1X
1X
1X
L
L
L
L
H
25 MHz
75 MHz
VCO/4
1X
1X
1X
2X
L
L
L
H
L
25 MHz
75 MHz
VCO/4
1X
1X
2X
2X
L
L
L
H
H
25 MHz
75 MHz
VCO/4
1X
2X
2X
2X
L
L
H
L
L
25 MHz
75 MHz
VCO/4
2X
2X
2X
2X
L
L
H
L
H
16.67 MHz
50 MHz
VCO/6
1X
1X
1X
3X
L
L
H
H
L
16.67 MHz
50 MHz
VCO/6
1X
1X
3X
3X
L
L
H
H
H
16.67 MHz
50 MHz
VCO/6
1X
3X
3X
3X
L
H
L
L
L
16.67 MHz
50 MHz
VCO/6
3X
3X
3X
3X
L
H
L
L
H
50 MHz
150 MHz
VCO/2
1X
1X
1X
1/2X
L
H
L
H
L
50 MHz
150 MHz
VCO/2
1X
1X
1/2X
1/2X
L
H
L
H
H
50 MHz
150 MHz
VCO/2
1X
1/2X
1/2X
1/2X
L
H
H
L
L
50 MHz
150 MHz
VCO/2
1/2X
1/2X
1/2X
1/2X
L
H
H
L
H
50 MHz
150 MHz
VCO/2
1X
1X
1X
1/3X
L
H
H
H
L
150 MHz
VCO/2
1X
1X
1/3X
1/3X
L
H
H
H
H
50 MHz
150 MHz
VCO/2
1X
1/3X
1/3X
1/3X
NOTE 1: Minimum and maximum input frequency and FBOUT frequency depend on the configuration of the SELn inputs.
P
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