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參數(shù)資料
| 型號： | CDC338 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Phase-lock Loop Clock Driver with 3 state Output(鎖相環(huán)時(shí)鐘驅(qū)動器(三態(tài)輸出)) |
| 中文描述： | 鎖相3態(tài)輸出環(huán)路時(shí)鐘驅(qū)動器（鎖相環(huán)時(shí)鐘驅(qū)動器（三態(tài)輸出）） |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 153K |
| 代理商： | CDC338 |
CDC338
PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS418 – MAY 1992 – REVISED FEBRUARY 1993
Copyright
1993, Texas Instruments Incorporated
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Replaces SN74ABT338
Low Output Skew, Low Pulse Skew for
Clock-Distribution and Clock-Generation
Applications
State-of-the-Art EPIC-
ΙΙ
B
BiCMOS
Design Significantly Reduces Power
Dissipation
TTL-Compatible Inputs and TTL Outputs
Distributes One Clock Input to Six Outputs
– Four Same-Frequency Outputs
– One Half-Frequency Outputs
– One Double-Frequency Output
Output Duty Cycle Correction to 50%
No External RC Network Required
Edge-Triggered Clear for Half-Frequency
Output
Distributed V
CC
and Ground Pins Reduce
Switching Noise
High-Drive Outputs (–48-mA I
OH
,
48-mA I
OL
)
Packaged in Plastic Small-Outline Package
description
The CDC338 is a high-performance, low-skew, low-jitter clock driver. It uses phase-lock loops (PLLs) to
precisely align, in both frequency and phase, the clock output signals to the clock (CLKIN) input signal. It is
specifically designed for use with popular microprocessors operating at speeds from 15 MHz to 35 MHz or up
to 70 MHz using the double-frequency (DF) output.
The four Y outputs switch in phase and at the same frequency as CLKIN. The half-frequency (HF) output
operates at one-half the CLKIN frequency, and DF operates at twice the CLKIN frequency. All output signal duty
cycles are adjusted to 50% independent of the duty cycle at CLKIN.
Output-enable (OE) and clear (CLR) inputs are also provided for output control and synchronization. When OE
is high, the outputs are in the high-impedance state. When OE is low, the outputs are active. The CLR input is
negative-edge-triggered and is provided to allow phase synchronization of the HF outputs on multiple CDC338
devices.
Unlike many products containing PLLs, the CDC338 does not require external RC networks. The loop filter for
each PLL is included on chip, minimizing component count, board space, and cost. Additionally, each output
has its own PLL, which allows mismatches between loads from one output to another.
Because it is based on PLL circuitry, the CDC338 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required following power up and application
of a fixed-frequency, fixed-phase signal at CLKIN as well as following any changes to the PLL reference or
feedback signals. Such changes occur upon phase reset of the HF output and upon enable of all outputs.
Therefore, stabilization is also required following high-to-low transitions on either CLR or OE.
The CDC338 is characterized for operation from –40
°
C to 85
°
C.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
Y1
GND
Y2
GND
V
CC
Y3
GND
Y4
V
CC
OE
V
CC
DF
V
CC
CLKIN
GND
HF
V
CC
CLR
V
CC
DW PACKAGE
(TOP VIEW)
EPIC-
ΙΙ
B is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
P
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDC338DW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Six Distributed-Output Clock Driver |
| CDC339 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:CLOCK DRIVER WITH 3-STATE OUTPUTS |
| CDC339DB | 功能描述:時(shí)鐘驅(qū)動器及分配 1-To-8 Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDC339DBG4 | 功能描述:時(shí)鐘驅(qū)動器及分配 1-To-8 Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDC339DBLE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:CLOCK DRIVER WITH 3-STATE OUTPUTS |
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