- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379830 > CDC2587 (Texas Instruments, Inc.) Octal Divided -by-2 Circuit/Clock Driver(3.3V鎖相環(huán)時鐘驅(qū)動器(三態(tài)輸出)) PDF資料下載
參數(shù)資料
| 型號： | CDC2587 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Octal Divided -by-2 Circuit/Clock Driver(3.3V鎖相環(huán)時鐘驅(qū)動器(三態(tài)輸出)) |
| 中文描述： | 八路分裂的× 2電路/時鐘驅(qū)動器（3.3鎖相環(huán)時鐘驅(qū)動器（三態(tài)輸出）） |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 163K |
| 代理商： | CDC2587 |
CDC2587
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS560B – DECEMBER 1995 – REVISED JULY 1996
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
CLKIN
1
I
Clock input. CLKIN provides the clock signal to be distributed by the CDC2587 clock-driver circuit.
CLKIN is used to provide the reference signal to the integrated PLL that generates the clock output
signals. CLKIN must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once
the circuit is powered up and a valid CLKIN signal is applied, a stabilization time is required for the
PLL to phase lock the feedback signal to its reference signal.
FBIN
3
I
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN should be wired to
FBOUT. The integrated PLL adjusts the output clocks to obtain zero phase delay between the
FBIN and CLKIN inputs.
VREF
2
I
Voltage reference. VREF is the reference voltage required for SSTL operation. A nominal voltage
of 1.5 V should be applied when SSTL operation of the CLKIN and FBIN signals is required. If VREF
is strapped to GND, CLKIN and FBIN operate at TTL switching levels.
OE
30
I
Output enable. OE is the output enable for all of the Y outputs. When OE is low, all Y outputs are
enabled. When OE is high, all Y outputs are in the high-impedance state. FBOUT is not disabled
by OE, therefore the PLL is not disrupted when placing the Y outputs into the high-impedance
state.
TEST
31
I
Test input. TEST is used to bypass the PLL circuitry for factory testing of the device. When TEST
is low, all outputs operate using the PLL circuitry. When TEST is high, the device is placed in a test
mode that bypasses the PLL circuitry.
RESET
32
I
Reset input. RESET is used to reset the counter circuit that divides the VCO output frequency. Y
outputs configured as fractional frequencies of the input signal may be reset to a known state.
RESET is a negative-edge-triggered signal. When a high-to-low edge occurs at RESET, the
counter that divides the VCO output signal is asynchronously cleared to a low level.
SEL(0:3)
28–25
I
Select inputs. SEL(0:3) configure the frequency of the Y outputs in banks of four.
1Y(0:3)
2Y(0:3)
3Y(0:3)
4Y(0:3)
8, 9, 12, 13
16, 17, 20, 21
36, 37, 40, 41
44, 45, 48, 49
O
Clock outputs. These output pins are configured by SEL(0:3) to transmit a multiple or fraction of
the input frequency. The relationship between the CLKIN frequency and the output frequency is
dependent on the select inputs. Due to normal operation of the PLL, the duty cycle of the Y output
signals is nominally 50%, independent of the duty cycle of CLKIN. All outputs provide integrated
25-
series-damping resistors to improve signal integrity at the load.
FBOUT
5
O
Feedback output. FBOUT is synchronized in phase and frequency to the input clock. FBOUT is
not a 3-state output and is not disabled when OE is asserted low. A stabilization time is required
on power up and the application of a fixed frequency, fixed-phase signal at CLKIN. In addition, the
stabilization time may be required when changes occur to the input signal or the states of the
SEL(0:3) control inputs.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
Input voltage range, V
I
(see Note 2)
Voltage range applied to any output in the high state
or power-off state, V
O
(see Note 2)
Current into any output in the low state, I
O
Input clamp current, I
IK
(V
I
< 0)
Output clamp current, I
OK
(V
O
< 0)
Maximum power dissipation at T
A
= 55
°
C (in still air) (see Note 3)
Storage temperature range, T
stg
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature of 150
°
C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerationsapplication note in the ABT Advanced BiCMOS Technology Data
Book, iterature number SCBD002.
–0.5 V to 4.6 V
–0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–0.5 V to V
CC
+
0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24 mA
–20 mA
–50 mA
1.2 W
–65
°
C to 150
°
C
P
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDC303 | "1-To-8 |
| CDC3244 | 3.3-V ABT Octal Clock Driver with 3 State Output(3.3VABT八時鐘驅(qū)動器(三態(tài)輸出)) |
| CDC328ADB | ECONOLINE: RSZ/P - 1kVDC |
| CDC330 | Clock Driver with 3 state Output(時鐘驅(qū)動器(三態(tài)輸出)) |
| CDC338 | Phase-lock Loop Clock Driver with 3 state Output(鎖相環(huán)時鐘驅(qū)動器(三態(tài)輸出)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDC2587DGGR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Sixteen Distributed-Output Clock Driver |
| CDC-25PF | 制造商:HRS 制造商全稱:HRS 功能描述:CD CRIMP TYPE CONNECTOR |
| CDC-25SF | 制造商:HRS 制造商全稱:HRS 功能描述:CD CRIMP TYPE CONNECTOR |
| CDC303 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER |
| CDC303D | 功能描述:時鐘驅(qū)動器及分配 1-8,Divide-By-2 Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。