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參數(shù)資料
| 型號： | CDC2587 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Octal Divided -by-2 Circuit/Clock Driver(3.3V鎖相環(huán)時鐘驅(qū)動器(三態(tài)輸出)) |
| 中文描述： | 八路分裂的× 2電路/時鐘驅(qū)動器（3.3鎖相環(huán)時鐘驅(qū)動器（三態(tài)輸出）） |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 163K |
| 代理商： | CDC2587 |
CDC2587
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS560B – DECEMBER 1995 – REVISED JULY 1996
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 5)
MIN
16.67
MAX
UNIT
f l
fclock
Input clock frequency
VCO is operating at six times the CLKIN frequency
50
MHz
VCO is operating at four times the CLKIN frequency
25
75
VCO is operating at two times the CLKIN frequency
50
150
Input clock duty cycle
40%
60%
After OE
↓
After SELn
After power up and CLKIN
5
Stabilization time
5
5
s
μ
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications for propagation delay
and skew parameters given in the switching characteristics table are not applicable.
NOTE 5: Preliminary specifications are based on SPICE analysis.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 30 pF (see Note 6 and Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
TYP
MAX
UNIT
fmax
tphase error
tsk(o) same frequency
tsk(o) different frequency
Jitter (peak to peak)
150
MHz
CLKIN
↑
FBIN
↑
–300
+300
ps
Y
250
ps
500
CLKIN
↑
Y
↑
–75
+75
ps
Duty cycle
Y
45%
55%
tr
tf
ns
ns
NOTE 6: The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, V
REF
= V
TT
= V
CC
×
0.45, C
L
= 30 pF (see Note 6 and Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
TYP
MAX
UNIT
fmax
tphase error
tsk(o) same frequency
tsk(o) different frequency
Jitter (peak to peak)
150
MHz
CLKIN
↑
FBIN
↑
–300
+300
ps
Y
250
ps
500
CLKIN
↑
Y
↑
–75
+75
ps
Duty cycle
Y
45%
55%
tr
tf
ns
ns
NOTE 6:
The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
P
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