參數(shù)資料
型號(hào): CDB42L51
廠商: Cirrus Logic Inc
文件頁(yè)數(shù): 33/43頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL FOR CS42L51 CODEC
標(biāo)準(zhǔn)包裝: 1
主要目的: 音頻編解碼器
嵌入式: 是,其它
已用 IC / 零件: CS42L51,CS8406,CS8415
主要屬性: 立體聲數(shù)字音頻發(fā)射器和接收器
次要屬性: 圖形用戶(hù)界面,S/PDIF 接口
已供物品: 板,CD
相關(guān)產(chǎn)品: CS42L51-DNZR-ND - IC CODEC STEREO W/HDPN AMP 32QFN
598-1627-ND - IC CODEC STEREO W/HDPN AMP 32QFN
CS42L51-CNZR-ND - IC CODEC LOW-V 24BIT 32-QFP
598-1045-ND - IC CODEC STEREO W/HDPN AMP 32QFN
其它名稱(chēng): 598-1005
DS679F1
39
CS42L51
4.5.1
Slave
LRCK and SCLK are inputs in Slave Mode. The speed of the CODEC is automatically determined based
on the input MCLK/LRCK ratio when the Auto-Detect function is enabled. Certain input clock ratios will
then require an internal divide-by-two of MCLK* using either the MCLKDIV2 bit or the MCLKDIV2 stand-
alone control pin.
Additional clock ratios are allowed when the Auto-Detect function is disabled; but the appropriate speed
mode must be selected using the SPEED[1:0] bits.
4.5.2
Master
LRCK and SCLK are internally derived from the internal MCLK (after the divide, if MCLKDIV2 is enabled).
In Hardware Mode the CODEC operates in single-speed only. In Software Mode, the CODEC operates
in either quarter-, half-, single- or double-speed depending on the setting of the SPEED[1:0] bits.
Auto-Detect
QSM
HSM
SSM
DSM
Disabled
(Software
Mode only)
512, 768, 1024, 1536,
2048, 3072
256, 384, 512, 768,
1024, 1536
128, 192, 256, 384,
512, 768
128, 192, 256, 384
Enabled
1024, 1536, 2048*,
3072*
512, 768, 1024*, 1536*
256, 384, 512*, 768*
128, 192, 256*, 384*
*MCLKDIV2 must be enabled.
Table 3. MCLK/LRCK Ratios
÷ 256
÷ 128
÷ 512
LRCK Output
(Equal to Fs)
Single
Speed
Quarter
Speed
Half
Speed
01
10
11
SCLK Output
÷ 2
÷ 1
0
1
MCLK
MCLKDIV2
÷ 128
00
÷ 4
÷ 2
÷ 8
Single
Speed
Quarter
Speed
Half
Speed
01
10
11
÷ 2
00
Double
Speed
Double
Speed
SPEED[1:0]
Figure 17. Master Mode Timing
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