參數(shù)資料
型號(hào)： CDB391A
廠商： Cirrus Logic, Inc.
英文描述： 24-BIT, 192 kHz STEREO DAC WITH VOLUME CONTROL
中文描述： 24位192千赫立體聲DAC控制音量
文件頁(yè)數(shù)： 34/40頁(yè)
文件大?。?/td> 748K
代理商： CDB391A
CS4391A
34
DS600PP3
8. CONTROL PORT INTERFACE
The control port is used to load all the internal set-
tings of the CS4391A. The operation of the control
port may be completely asynchronous to the audio
sample rate. However, to avoid potential interfer-
ence problems, the control port pins should remain
static if no operation is required.
The control port has 2 modes: SPI and I
2
C, with the
CS4391A operating as a slave device in both
modes. If I
2
C operation is desired, AD0/CS should
be tied to VA or AGND. If the CS4391A ever de-
tects a high to low transition on AD0/CS after pow-
er-up, SPI mode will be selected. The control port
registers are write-only in SPI mode.
8.1
In SPI mode, CS is the CS4391A chip select signal,
CCLK is the control port bit clock, CDIN is the in-
put data line from the microcontroller and the chip
address is 0010000. All signals are inputs and data
is clocked in on the rising edge of CCLK.
SPI Mode
Figure 16 shows the operation of the control port in
SPI mode. To write to a register, bring CS low. The
first 7 bits on CDIN form the chip address, and
must be 0010000. The eighth bit is a read/write in-
dicator (R/W), which must be low to write. The
next 8 bits form the Memory Address Pointer
(MAP), which is set to the address of the register
that is to be updated. The next 8 bits are the data
which will be placed into the register designated by
the MAP. See Table 16.
The CS4391A has MAP auto increment capability,
enabled by the INCR bit in the MAP register. If
INCR is 0, then the MAP will stay constant for suc-
cessive writes. If INCR is set to 1, then MAP will
auto increment after each byte is written, allowing
block reads or writes of successive registers.
I
2
C Mode
In I
2
C mode, SDA is a bi-directional data line. Data
is clocked into and out of the part by the clock,
SCL, with the clock to data relationship as shown
in Figure 3. There is no CS pin. Pin AD0 forms the
partial chip address and should be tied to VA or
AGND as required. The upper 6 bits of the 7-bit ad-
dress field must be 001000. To communicate with
the CS4391A the LSB of the chip address field,
which is the first byte sent to the CS4391A, should
match the setting of the AD0 pin. The eighth bit of
the address byte is the R/W bit (high for a read, low
for a write). If the operation is a write, the next byte
is the Memory Address Pointer, MAP, which se-
lects the register to be read or written. The MAP is
then followed by the data to be written. If the op-
eration is a read, then the contents of the register
pointed to by the MAP will be output after the chip
address.
8.2
The CS4391A has MAP auto increment capability,
enabled by the INCR bit in the MAP register. If
INCR is 0, then the MAP will stay constant for suc-
cessive writes. If INCR is set to 1, then MAP will
auto increment after each byte is written, allowing
block reads or writes of successive registers.
For more information on I
2
C, please see “The I2C-
Bus Specification: Version 2.0”, listed in the Ref-
erences section.
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