參數(shù)資料
型號: CDB391A
廠商: Cirrus Logic, Inc.
英文描述: 24-BIT, 192 kHz STEREO DAC WITH VOLUME CONTROL
中文描述: 24位192千赫立體聲DAC控制音量
文件頁數(shù): 29/40頁
文件大?。?/td> 748K
代理商: CDB391A
CS4391A
DS600PP3
29
Note:These clocking ratios are only available inControl Port Mode when the MCLK Divide bit is enabled.
Sample Rate
(kHz)
32
44.1
48
MCLK (MHz)
See Note
1024x
32.7680
45.1584
49.1520
256x
8.1920
11.2896
12.2880
Table 8. Single Speed (4 to 50 kHz sample rates) Common Clock Frequencies
384x
12.2880
16.9344
18.4320
512x
16.3840
22.5792
24.5760
768x
24.5760
33.8688
36.8640
Sample Rate
(kHz)
64
88.2
96
MCLK (MHz)
See Note
512x
32.7680
45.1584
49.1520
128x
8.1920
11.2896
12.2880
192x
12.2880
16.9344
18.4320
256x
16.3840
22.5792
24.5760
384x
24.5760
33.8688
36.8640
Table 9. Double Speed (50 to 100 kHz sample rates) Common Clock Frequencies
Sample Rate
(kHz)
176.4
192
MCLK (MHz)
See Note
256x
45.1584
49.1520
64x
96x
128x
22.5792
24.5760
192x
33.8688
36.8640
11.2896
12.2880
16.9344
18.4320
Table 10. Quad Speed (100 to 200 kHz sample rates) Common Clock Frequencies
M3
M1
(DIF1)
0
0
1
1
Table 11. Single Speed (4 to 50 kHz) Digital Interface Format, Stand-Alone Mode Options
M0
(DIF0)
0
1
0
1
DESCRIPTION
FORMAT
FIGURE
0
0
0
0
Left Justified, up to 24-bit data
I
2
S, up to 24-bit data
Right Justified, 16-bit Data
Right Justified, 24-bit Data
0
1
2
3
7
8
9
10
M3
M2
(DEM)
0
1
Table 12. Single Speed Only (4 to 50 kHz) De-Emphasis, Stand-Alone Mode Options
DESCRIPTION
FIGURE
0
0
No De-Emphasis
De-Emphasis Enabled
13
13
M3
1
1
M2
0
0
M1
0
0
M0
0
1
DESCRIPTION
FORMAT
0
1
FIGURE
7
8
Left Justified up to 24-bit data
I
2
S up to 24-bit data
Right Justified 16-bit data
Right Justified 24-bit data
1
1
0
0
1
1
0
1
2
3
9
10
Table 13. Double Speed (50 to 100 kHz) Digital Interface Format, Stand-Alone Mode Options
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