參數(shù)資料
型號: CDB391A
廠商: Cirrus Logic, Inc.
英文描述: 24-BIT, 192 kHz STEREO DAC WITH VOLUME CONTROL
中文描述: 24位192千赫立體聲DAC控制音量
文件頁數(shù): 21/40頁
文件大小: 748K
代理商: CDB391A
CS4391A
DS600PP3
21
4.5.5
Freeze (Bit 2)
Function:
This function allows modifications to the registers without the changes being taking effect until Freeze
is disabled. To make multiple changes in the Control port registers take effect simultaneously, set the
Freeze Bit, make all register changes, then Disable the Freeze bit.
4.5.6
Master Clock Divide (Bit 1)
Function:
This function allows the user to select an internal divide by 2 of the Master Clock. This selection is
required to access the higher Master Clock rates as shown in Table 9.
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