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參數(shù)資料
| 型號： | C9821GQ |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | 單時鐘驅(qū)動器| SSOP封裝| 24針|塑料 |
| 文件頁數(shù)： | 4/18頁 |
| 文件大小： | 121K |
| 代理商： | C9821GQ |
Direct Rambus
Plus Clock Generator
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07092 Rev. **
05/03/2001
Page 4 of 18
APPROVED PRODUCT
C9821
System Clock Configuration (Cont.)
After comparing the phases of Pclk/M and SynClk/N, the C9821 Phase Detector drives a phase aligner that adjusts
the phase of the C9821 output clock, busclk. Since the other elements in the distributed loop have a fixed delay,
adjusting Busclk adjusts the phase of SynClk and thus the phase of SynClk/N.
In this manner, the distributed loop adjusts the phase of SynClk/N to match that of Pclk/M, eliminating the phase
error at the input of the C9821. When the clocks are aligned, data can be exchanged directly from the Pclk domain to
the SynClk domain.
The Gear Ratio Logic supports four clock ratios (1.0, 1.33, 1.5), where the ratio is defined as the ratio of Pclk/SynClk.
Since Busclk - 4*synClk, this ratio also is equal to 4*Pclk/busclk.
In addition, the device is able to receive input signals that are generated from different voltage power supplies. The
controller output voltage supply is connected to the pin VDDIPD of the C9821, and is used as the reference for the
two-phase detector input signal, PclkM and SynClkN. The output voltage supply is also used as the reference for the
output enable/disable signal, StopB.
The reference clock comes from the main clock source chip. The main clock source output voltage supply is
connected to the pin VDDlR of C9821, and is used as the reference for the Refclk input signal.
Table of Frequencies and Gear Ratios
Gear Ratio Timing Diagram
Pclk
SynClk
Pclk/M =
SynClk/N
Figure: 4
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