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參數(shù)資料
| 型號： | C9821GQ |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | 單時鐘驅(qū)動器| SSOP封裝| 24針|塑料 |
| 文件頁數(shù)： | 13/18頁 |
| 文件大小： | 121K |
| 代理商： | C9821GQ |
Direct Rambus
Plus Clock Generator
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07092 Rev. **
05/03/2001
Page 13 of 18
APPROVED PRODUCT
C9821
Device Parameters
Characteristic
Output Duty Cycle over 10,000 cycles
Clock cycle time
Jitter over 1-6 clock cycles at 400 MHz
a
Jitter over 1-6 clock cycles at 356 MHz
a
Jitter over 1-6 clock cycles at 300 MHz
a
Jitter over 1-6 clock cycles at 267 MHz
a
Phase Aligner phase step size (at Clk/ClkB)
Phase Detector phase error for distributed loop
Measured at PcklM-SynclkN (rising edges) (does not
include clock Jitter)
PLL output phase error when tracking SSC
Output voltage during Clk Stop (StopB=0)
Output crossing-point voltage
Output voltage swing
b
Output high voltage
Output low voltage
Output dynamic resistance (at pins)
c
Output current during Hi-Z (S0=1, S1=1)
Output current during Clk Stop (StopB=0)
Cycle-to-cycle duty cycle error at 400 MHz
Cycle-to-cycle duty cycle error at 300 MHz
Cycle-to-cycle duty cycle error at 267 MHz
Output rise and fall times (measured at 20% - 80% of
output voltage)
Difference between rise and fall times on the same
pin of a single device (20% - 80%)
Symbol
DC
t
CYCLE
Min
40%
2.5
-
-
-
-
2
-100
Typ
50%
Max
60%
3.75
100
140
140
160
Units
t cycle
nS
pS
pS
pS
pS
pS
pS
Conditions
-
tj
t
STEP
t
ERR,PD
-
100
t
ERR,SSC
V
X,STOP
V
X
V
COS
V
OH
V
OL
R
OUT
I
OZ
I
OZ,STOP
-100
1.1
1.3
0.4
-
1.0
12
-
-
-
-
-
160
-
-
-
-
-
-
-
-
100
2.0
1.8
0.6
2.0
-
50
50
500
50
70
80
400
pS
V
V
V
V
V
μ
A
μ
A
pS
pS
pS
pS
-
-
-
-
t
DC,ERR
t
CR,
t
CF
t
CR,
t
CF
-
100
pS
=3.3V
±
5
%, TA = 0oC to +70oC
a. Output short-term jitter spec is peak to peak.
b. V
COS
= V
OH
– V
OL
c. R
OUT
=
V
O
/
I
O
. This is defined at the output pins, not at the measurement point.
Table 11: Device Characteristics
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