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參數(shù)資料
| 型號： | C9832HT |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | CPU系統(tǒng)時鐘發(fā)生器|采用TSSOP | 56PIN |塑料 |
| 文件頁數(shù)： | 1/24頁 |
| 文件大?。?/td> | 169K |
| 代理商： | C9832HT |
C9832H
High Performance Pentium 4 Clock Synthesizer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07109 Rev. **
5/24/2001
Page 1 of 24
Approved Product
Product Features
Supports Pentium
4 type CPUs
3.3 Volt Power supply
10 copies of PCI clocks
3 differential CPU clocks
SMBus Support with read back capabilities
Spread Spectrum EMI Reduction
Dial-a-Frequency features
Dial-a-dB features
56 Pin SSOP and TSSOP package
Frequency Table
S2
S1
S0
CPU
(0:2)
66M
100M
200M
133M
66M
100M
200M
133M
Hi-Z
TCLK/2
3V66
66BUFF(0:2)/
3V66(0:4)
66IN
66IN
66IN
66IN
66M
66M
66M
66M
Hi-Z
TCLK/4
66IN/
3V66-5
PCI_F
PCI
66IN/2
66IN/2
66IN/2
66IN/2
33 M
33 M
33 M
33 M
Hi-Z
TCLK/8
REF
USB/
DOT
48M
48M
48M
48M
48M
48M
48M
48M
Hi-Z
TCLK/2
1
1
1
1
0
0
0
0
M
M
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
66M
66M
66M
66M
66M
66M
66M
66M
Hi-Z
TCLK/4
66MHz clock input
66MHz clock input
66MHz clock input
66MHZ clock input
66M
66M
66M
66M
Hi-Z
TCLK/4
14.318M
14.318M
14.318M
14.318M
14.318M
14.318M
14.318M
14.318M
Hi-Z
TCLK
Note:
TCLK is a test clock over driven on the XTAL_IN input during test mode. M= driven to a level between 1.0 and 1.8 Volts
If the S2 pin is at a M level during power up, a 0 state will be latched into the devices internal state register.
Block Diagram
Pin Configuration
PLL1
PLL2
/2
WD
Logic
Power
Up Logic
XIN
XOUT
CPU_STP#
IREF
VSSIREF
S(0:2)
MULT0
VTT_PG#
PCI_STP#
PD#
SDATA
SCLK
VDDA
66B[1:3]/3V66[2:5]
48M DOT
48M USB
PCI(0:2,4:6)
PCI_F(0:2)
3V66_1/VCH
3V66_0
CPU/(0:2)
CPU(0:2)
REF
66IN/3V66-5
I2C
Logic
PCIE
VDD
XIN
XOUT
VSS
PCIF0
PCIF1
PCIF2
VDD
VSS
PCI0
PCI1
PCI2
PCIE
VDD
VSS
PCI4
PCI5
PCI6
VDD
VSS
66B0/3V66_2
66B1/3V66_3
66B2/3V66_4
66IN/3V66_5
PD#
VDDA
VSSA
VTT_PG#
REF
S1
S0
CPU_STP#
CPU0
CPU/0
VDD
CPU1
CPU/1
VSS
VDD
CPU2
CPU/2
MULT0
IREF
VSSIREF
S2
48MUSB
48MDOT
VDD
VSS
3V66_1/VCH
PCI_STP#
3V66_0
VDD
VSS
SCLK
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
C
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