- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379723 > C9630CY (CYPRESS SEMICONDUCTOR CORP) PC133 Clock Generator for SiS630/Pentium III & SiS540/Socket7 Applications PDF資料下載
| 型號： | C9630CY |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PC133 Clock Generator for SiS630/Pentium III & SiS540/Socket7 Applications |
| 中文描述： | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 2/18頁 |
| 文件大?。?/td> | 185K |
| 代理商： | C9630CY |
PC133 Clock Generator for SiS630/Pentium
III & SiS540/Socket7 Applications
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07035 Rev. **
05/02/2001
Page 2 of 18
APPROVED PRODUCT
C9630
Pin Description
PIN No.
2
Pin Name
S3/ REF0
PWR
VDD
I/O
I/O
Description
3.3V 14.318 MHz clock output. This Is a power on bi-directional pin.
During power up, this pin is an input
“
S3
”
for setting the CPU
frequency (see table1, page 1) (see app note, page 5). When the
power reaches the rail, this pin becomes a buffered output of the
signal applied at Xin (typically 14.318 MHz).
This pin is a buffered output of the signal applied at Xin (typically
14.318)
14.318MHz Crystal input
14.318MHz Crystal output
This is a power on bi-directional pin. During power up, this pin is an
input
“
S1
”
for setting the CPU frequency (see table1, page 1) (see
app not, page 5). When the power reaches the rail, this pin becomes
a PCI0 clock output.
This is a power on bi-directional pin. During power up, this pin is an
input
“
S2
”
for setting the CPU frequency (see table1, page 1) (see
app not, page 5). When the power reaches the rail, this pin becomes
a PCI1 clock output.
3.3V PCI clock outputs.
48
REF1
VDD
O
4
5
7
XIN
XOUT
S1/ PCI0*
VDD
VDD
VDD
I
O
I/O
8
S2/ PCI1*
VDD
I/O
9,11,12,13,
14
25
PCI(2:6)
VDD
O
24/48MHz
VDD
O
This pin is programmable to 24MHz or 48 MHz clock output through
SMBus. It defaults to 24MHz at power up.
This is a power on bi-directional pin. During power up, this pin is an
input
“
S0
”
for setting the CPU frequency (see table1, page 1) (see
app note, page 5). When the power reaches the rail, this pin becomes
a 48MHz clock output. This clock conforms to the USB spec. of
+167ppm.
SMBus compatible SDATA input. Has an internal pull-up (>100K
)
SMBus compatible SCLK input. Has an internal pull-up (>100K
)
3.3V SDRAM clock outputs. See table1, p.1 for frequency selection.
26
S0 / 48MHz*
VDD
I/O
28
29
SDATA
SCLK
SDRAM(0:13)
VDD
VDD
VDD
I
I
17,18,20,21,
28,29,31,32,
34,35,37,38,
40,41
43,45,46
O
CPU(0:2)
VDDC
O
2.5V or 3.3V Host bus clock outputs. See table 1, page 1 for
frequency selection.
3.3V Common Power Supply
1,6,15,19,
27, 30,36,42
47
3,10,16,22,
33,39,44
A bypass capacitor (0.1
μ
F) should be placed as close as possible to each positive power pin. If these bypass capacitors
are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
*Note: These pins have pulldown resistors, typical value 250
.
VDD
-
VDDC
VSS
-
-
2.5V or 3.3V Power Supply
’
s for CPU (0:2) clock outputs.
Common Ground pin.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| C9692 | PHOTON DETECTION UNIT |
| C9728DK-10 | Flat panel sensor Cassette type X-ray sensor with USB 2.0 interface |
| C9730DK-10 | Large area soft X-ray imaging, high resolution |
| C9732DK | Flat panel sensor Large area/soft X-ray imaging, high resolution |
| C9744 | PHOTON COUNTING UNIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| C963P | 制造商:PERKINELMER 制造商全稱:PerkinElmer Optoelectronics 功能描述:CHANNEL PHOTO MULTIPLIER |
| C96409-000 | 制造商:TE Connectivity 功能描述:55 CABLE - Cable Rools/Shrink Tubing 制造商:TE Connectivity 功能描述:55A6053-26-MST4-9CS2275 |
| C96433-000 | 功能描述:熱收縮管和套管 NT-MIL-1/4-0-SP RoHS:否 制造商:3M Electronic Specialty 類型:Tubing 材料:Polyolefin, Flexible 顏色:Clear 最低收縮溫度:+ 100 C 恢復(fù)直徑: 長度:100 ft 內(nèi)徑:1.5 in 收縮率:2:1 |
| C96465-000 | 制造商:TE Connectivity 功能描述:55PC4223-16-9/96-9CS2861 - Bulk |
| C96480-000 | 制造商:TE Connectivity 功能描述:82A0112-10-6 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。