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參數(shù)資料
| 型號： | C9630CY |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PC133 Clock Generator for SiS630/Pentium III & SiS540/Socket7 Applications |
| 中文描述： | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 12/18頁 |
| 文件大?。?/td> | 185K |
| 代理商： | C9630CY |
PC133 Clock Generator for SiS630/Pentium
III & SiS540/Socket7 Applications
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07035 Rev. **
05/02/2001
Page 12 of 18
APPROVED PRODUCT
C9630
DC Parameters
Characteristic
Input Low Voltage
Input High Voltage
Input Low Current (@VIL = VSS)
Input High Current (@VIL =VDD)
Tri-State leakage Current
Dynamic Supply Current
Dynamic Supply Current
Input pin capacitance
Output pin capacitance
Pin inductance
Crystal pin capacitance
Symbol
VIL2
VIH2
IIL
IIH
Ioz
Idd3.3V
Idd2.5V
Cin
Cout
Lpin
Xin/Xout
Min
Typ
Max
Units
Vdc
Vdc
μA
μA
μA
mA
mA
pF
pF
nH
pF
Conditions
-
-
-
1.0
-
-5
5
10
400
100
5
6
7
34
2.2
Note 2
66
-
-
-
-
-
-
30
For internal Pull down resistors,
Notes 1,3
-
-
-
-
-
-
S(3:0) = 0101, Note 4
S(3:0) = 0111, Note 4
32
Measured from Pin to Ground.
Note 5
Crystal DC Bias Voltage
Crystal Startup time
V
BIAS
Txs
0.3Vdd
-
Vdd/2
-
0.7Vdd
40
V
μ
S
From Stable 3.3V power supply.
VDD = 3.3V
±
5
%, VDDC = 2.5
±
5%, TA = 0
o
to +70
o
C
Note1:
Note2:
Note3:
Note4:
Note5:
Applicable to S(0:3).
Applicable to Sdata, and Sclk.
Although internal pull-down resistors have a typical value of 250K, this value may vary between 200K and 500K.
All outputs loaded as per table 5 below.
Although the device will reliably interface with crystals of a 15pF
–
20pF C
L
range, it is optimized to interface with a typical C
L
= 16pF
crystal specifications.
Clock Name
CPU, REF
PCI, SDRAM
24MHz, 48MHz
Max Load (in pF)
20
30
15
Table 5
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