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參數(shù)資料
| 型號(hào)： | C9630CY |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PC133 Clock Generator for SiS630/Pentium III & SiS540/Socket7 Applications |
| 中文描述： | 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大小： | 185K |
| 代理商： | C9630CY |
PC133 Clock Generator for SiS630/Pentium
III & SiS540/Socket7 Applications
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07035 Rev. **
05/02/2001
Page 11 of 18
APPROVED PRODUCT
C9630
Spread Spectrum Clock Generation (SSCG) (Cont.)
In Center Spread mode, the Center frequency remains the same as in the non-spread mode.
Down Spread
Center Spread
Fig.8A
Fig.8B
Spread Spectrum Selection Table
SSTS
MBS 1
MBS 0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Table 4
Spread%
- 0.5
+/- 0.125
+/- 0.5
+/- 0.25
-0.5
+/- 0.125
+/- 0.5
See table 3, (default)
Maximum Ratings
Maximum Input Voltage Relative to VSS: VSS - 0.3V
Maximum Input Voltage Relative to VDD: VDD + 0.3V
Storage Temperature:
Operating Temperature:
Maximum ESD protection
Maximum Power Supply:
-65
o
C to + 150
o
C
0
o
C to +70
o
C
2KV
5.5V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
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