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| 型號(hào)： | C05M68HC05M |
| 廠商： | Motorola, Inc. |
| 英文描述： | HCMOS Microcontroller Unit |
| 中文描述： | HCMOS微控制器 |
| 文件頁(yè)數(shù)： | 80/130頁(yè) |
| 文件大小： | 1541K |
| 代理商： | C05M68HC05M |
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Analog Subsystem
Advance Information
MC68HC705P6A
—
Rev. 2.0
80
Analog Subsystem
MOTOROLA
9.5.3 Multi-Channel Operation
An input multiplexer allows the A/D converter to select from one of four
external analog signals. Port C pins PC3 through PC6 are shared with
the inputs to the multiplexer.
9.6 A/D Status and Control Register (ADSC)
The ADSC register reports the completion of A/D conversion and
provides control over oscillator selection, analog subsystem power, and
input channel selection. See
Figure 9-1
.
CC
—
Conversion Complete
This read-only status bit is set when a conversion sequence has
completed and data is ready to be read from the ADC register. CC is
cleared when the ADSC is written to or when data is read from the
ADC register. Once a conversion has been started, conversions of
the selected channel will continue every 32 internal clock cycles until
the ADSC register is written to again. During continuous conversion
operation, the ADC register will be updated with new data, and the CC
bit set every 32 internal clock cycles. Also, data from the previous
conversion will be overwritten regardless of the state of the CC bit.
ADRC
—
RC Oscillator Control
When ADRC is set, the A/D subsystem operates from the internal RC
oscillator instead of the internal clock. The RC oscillator requires a
time, t
RCON
, to stabilize before accurate conversion results can be
Address: $001E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
CC
ADRC
ADON
0
0
CH2
CH1
CH0
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-1. A/D Status and Control Register (ADSC)
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