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參數(shù)資料
| 型號(hào)： | C05M68HC05M |
| 廠商： | Motorola, Inc. |
| 英文描述： | HCMOS Microcontroller Unit |
| 中文描述： | HCMOS微控制器 |
| 文件頁數(shù)： | 48/130頁 |
| 文件大小： | 1541K |
| 代理商： | C05M68HC05M |
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Interrupts
Advance Information
MC68HC705P6A
—
Rev. 2.0
48
Interrupts
MOTOROLA
5.3.1 Reset Interrupt Sequence
The reset function is not in the strictest sense an interrupt; however, it is
acted upon in a similar manner as shown in
Figure 5-1
. A low-level input
on the RESET pin or internally generated RST signal causes the
program to vector to its starting address which is specified by the
contents of memory locations $1FFE and $1FFF. The I bit in the
condition code register is also set. The MCU is configured to a known
state during this type of reset as previously described in
Section 4.
Resets
.
5.3.2 Software Interrupt (SWI)
The SWI is an executable instruction. It is also a non-maskable interrupt
since it is executed regardless of the state of the I bit in the CCR. As with
any instruction, interrupts pending during the previous instruction will be
serviced before the SWI opcode is fetched. The interrupt service routine
address for the SWI instruction is specified by the contents of memory
locations $1FFC and $1FFD.
5.3.3 Hardware Interrupts
All hardware interrupts are maskable by the I bit in the CCR. If the I bit is
set, all hardware interrupts (internal and external) are disabled. Clearing
the I bit enables the hardware interrupts. Four hardware interrupts are
explained in the following subsections.
5.3.3.1 External Interrupt (IRQ)
The IRQ/V
PP
pin drives an asynchronous interrupt to the CPU. An edge
detector flip-flop is latched on the falling edge of IRQ/V
PP
. If either the
output from the internal edge detector flip-flop or the level on the
IRQ/V
PP
pin is low, a request is synchronized to the CPU to generate the
IRQ interrupt. If the LEVEL bit in the mask option register is clear (edge-
sensitive only), the output of the internal edge detector flip-flop is
sampled and the input level on the IRQ/V
PP
pin is ignored. The interrupt
service routine address is specified by the contents of memory locations
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