參數(shù)資料
型號: BX80532KC2800D
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 2800 MHz, MICROPROCESSOR
文件頁數(shù): 7/129頁
文件大?。?/td> 1640K
代理商: BX80532KC2800D
Intel Xeon Processor with 512 KB L2 Cache
104
Datasheet
Note:
The SMBus thermal sensor and its associated thermal diode are not related to, and are completely
independent of, the precision on-die temperature sensor and thermal control circuit (TCC) of the
Thermal Monitor feature discussed in Section 7.3.
The processor SMBus implementation uses the clock and data signals of the V1.1 System
Management Bus Specification. It does not implement the SMBSUS# signal. Layout and routing
guidelines are available in the appropriate platform design guidelines document.
For platforms which do not implement any of the SMBus features found on the processor, all of the
SMBus connections to the socket pins, except SM_VCC, may be left unconnected (SM_ALERT#,
SM_CLK, SM_DAT, SM_EP_A[2:0], SM_TS_A[1:0], SM_WP). SM_VCC provides power to the
VID generation logic in addition to supplying the SMBus and must be supplied with 3.3 volt power
to assure correct setting of the processor core voltage (VCC).
NOTE:
Actual implementation may vary. For use in general understanding of the architecture. All SMBus pull-up
and pull-down resistors are 10K ohms and located on the processor.
7.4.1
Processor Information ROM (PIROM)
The lower half (128 bytes) of the SMBus memory component is an electrically programmed read-
only memory with information about the processor. This information is permanently write-
protected. Table 44 shows the data fields and formats provided in the Processor Information ROM
(PIROM).
Figure 42. Logical Schematic of SMBus Circuitry
SM_EP_A1
Processor
Information
ROM
and
Scratch
EEPROM
(1 Kbit each)
Thermal
Sensor
A0
A1
A2
WP
A0
A1
SM_EP_A0
SM_EP_A2
SM_TS_A0
SM_TS_A1
SM_VCC
CLK
DATA
VCC
VSS
STDBY#
ALERT#
SM_CLK
SM_DAT
SM_ALERT#
SM_WP
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