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| 型號(hào)： | BX80532KC2800D |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 2800 MHz, MICROPROCESSOR |
| 文件頁(yè)數(shù)： | 71/129頁(yè) |
| 文件大?。?/td> | 1640K |
| 代理商： | BX80532KC2800D |
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Intel Xeon Processor with 512 KB L2 Cache
46
Datasheet
3.2
Front Side Bus Signal Quality Specifications and
Measurement Guidelines
Many scenarios have been simulated to generate a set of AGTL+ layout guidelines which are
available in the appropriate platform design guidelines.
Table 22 provides the signal quality specifications for all processor signals for use in simulating
signal quality at the processor pads.
Maximum allowable overshoot and undershoot specifications for a given duration of time are
low-to-high transitions and Figure 22 shows ringback tolerance for high-to-low transitions.
NOTES:
1. All signal integrity specifications are measured at the processor core (pads).
2. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
3. Specifications are for the edge rate of 0.3 - 4.0 V/nS at the receiver.
4. All values specified by design characterization.
5. Please see Section 3.0 for maximum allowable overshoot.
6. Ringback between GTLREF + 100 mV and GTLREF - 100 mV is not supported.
7. Intel recommends simulations not exceed a ringback value of GTLREF
± 200 mV to allow margin for other
sources of system noise
Figure 20. BCLK[1:0] Signal Integrity Waveform
Crossing
Voltage
Threshold
Region
VH
VL
Overshoot
Undershoot
Ringback
Margin
Rising Edge
Ringback
Falling Edge
Ringback,
BCLK0
BCLK1
Crossing
Voltage
Table 22. Ringback Specifications for AGTL+ and Asynchronous GTL+ Buffers
Signal Group
Transition
Maximum Ringback
(with Input Diodes Present)
Unit
Figure
Notes
AGTL+, Asynch GTL+
L
→ H
GTLREF + 0.100*GTLREF
V
1, 2, 3, 4, 5, 6, 7
AGTL+, Asynch GTL+
H
→ L
GTLREF - 0.100*GTLREF
V
1, 2, 3, 4, 5, 6, 7
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