參數(shù)資料
型號: BT849A
英文描述: Single-Chip Video Capture for PCI
中文描述: 單芯片的PCI視頻捕捉
文件頁數(shù): 97/141頁
文件大?。?/td> 1149K
代理商: BT849A
87
C
ONTROL
R
EGISTER
D
EFINITIONS
Command and Status Register
L848A_A
Bt848/848A/849A
Single-Chip Video Capture for PCI
Command and Status Register
PCI Configuration Header Location 0x04
The Command[15:0] register provides control over ability to generate and respond to PCI cycles. When a zero is writ-
ten to this register, Bt848 is logically disconnected from the PCI bus except for configuration cycles. The unused bits
in this register are set to a logical zero. The Status[31:16] register is used to record status information regarding PCI
bus related events.
Bits
Type
Default
Name
Description
[31]
RR
0
Detected Parity
Error
Set when a parity error is detected, in the address or data, regard-
less of the Parity Error Response control bit.
[30]
RR
0
Signaled
System Error
Set when SERR is asserted.
[29]
RR
0
Received
Master Abort
Set when master transaction is terminated with Master Abort.
[28]
RR
0
Received
Target Abort
Set when master transaction is terminated with Target Abort.
[27]
RR
0
Signaled Target
Abort
Set when target terminates transaction with Target Abort. This
occurs when detecting an address parity error.
[26:25]
RO
01
Address Decode
Time
Responds with medium DEVSEL timing.
[24]
RR
0
Data Parity
Reported
A value of 1 indicates that the bus master asserted PERR during
a read transaction or observed PERR asserted by target when
writing data to target. The Parity Error Response bit in the com-
mand register must have been enabled.
[23]
RO
1
FB2B Capable
Target capable of fast back-to-back transactions.
[8]
RW
0
SERR enable
A value of 1 enables the SERR driver.
[6]
RW
0
Parity Error
Response
A value of 1 enables parity error reporting.
[2]
RW
0
Bus Master
A value of 1 enables Bt848 to act as a bus initiator.
[1]
RW
0
Memory Space
A value of 1 enables response to Memory space accesses (target
decode to memory mapped registers).
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